# US 2025/0165254 A1 · Looping instruction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0165254 A1 - Document ID: US20250165254A1 - Status: Published application - Kind: A1 - Application number: 18/841,082 - Filed: 2023-01-25 - Published: 2025-05-22 - Earliest claimed: 2022-02-24 - Assignees: Xmos Ltd - Applicants: Xmos Ltd - Inventors: Hendrik Lambertus MULLER; Andrew STANFORD-JASON - Web page: https://patentgrep.com/patent/US20250165254A1 ## CPC - G06F 9/30065: {Loop control instructions; iterative instructions, e.g. LOOP, REPEAT} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30134: {Register stacks; shift registers} - G06F 9/381: {Loop buffering} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor (101) with an instruction set comprising a looping instruction and corresponding method are provided. The looping instruction is defined by a corresponding opcode and comprises a register operand for holding a sequence of subinstructions. The looping instruction causes the processor (101) to: repeatedly execute the looping instruction without incrementing a program counter, each execution of the looping instruction comprising: executing one of the subinstructions in the register operand; and modifying the register operand to contain a different set of subinstructions. ## Claims ### Claim 1 A processor configured to execute machine code instructions, each instruction being an instance of a predefined set of instruction types in an instruction set of the processor, wherein the instruction set includes a looping instruction defined by a corresponding opcode and comprising a register operand for holding a sequence of subinstructions, the looping instruction causing the processor to: repeatedly execute the looping instruction without incrementing a program counter, each execution of the looping instruction comprising: executing one of the subinstructions in the register operand; and modifying the register operand to contain a different set of subinstructions. ### Claim 2 (depends on 1) The processor according to claim 1, wherein modifying the register operand comprises shifting the subinstructions in the register operand. ### Claim 3 (depends on 1) The processor according to claim 1, wherein modifying the register operand comprises modifying the register operand to contain a smaller set of subinstructions. ### Claim 4 (depends on 3) The processor according to claim 3, wherein the looping instruction causes the processor to repeatedly execute the looping instruction until no subinstructions remain in the register operand. ### Claim 5 (depends on 1) The processor according to claim 1, wherein the subinstructions comprise at least a fetch subinstruction causing the processor to load values to the register operand. ### Claim 6 (depends on 1) The processor according to claim 1, wherein the subinstructions comprise at least a load subinstruction causing the processor to load values to a register of the processor. ### Claim 7 (depends on 1) The processor according to claim 1, wherein the subinstructions comprise at least a fetch-load subinstruction causing the processor to load values to the register operand and load other values to a register of the processor. ### Claim 8 (depends on 1) The processor according to claim 1, wherein the subinstructions comprise at least a multiply-accumulate subinstruction causing the processor to generate at least one result value by multiplying a respective first value by a respective second value, and to add the at least one result value to an accumulator in an output register of the processor. ### Claim 9 A method of executing a looping instruction, said looping instruction being one of a predefined set of instruction types in an instruction set of a processor, said looping instruction being defined by a corresponding opcode and comprising a register operand for holding a sequence of subinstructions, the method comprising: repeatedly executing the looping instruction without incrementing a program counter, each execution of the looping instruction comprising: executing one of the subinstructions in the register operand; and modifying the register operand to contain a different set of subinstructions. ### Claim 10 (depends on 9) The method according to claim 9, wherein modifying the register operand comprises shifting the subinstructions in the register operand. ### Claim 11 (depends on 9) The method according to claim 9, wherein modifying the register operand comprises modifying the register operand to contain a smaller set of subinstructions. ### Claim 12 (depends on 11) The method according to claim 11, comprising repeatedly executing the looping instruction until no subinstructions remain in the register operand. ### Claim 13 (depends on 9) The method according to claim 9, wherein the subinstructions comprise at least a fetch subinstruction comprising loading values to the register operand. ### Claim 14 (depends on 9) The method according to claim 9, wherein the subinstructions comprise at least a load subinstruction comprising loading values to a register of the processor. ### Claim 15 (depends on 9) The method according to claim 9, wherein the subinstructions comprise at least a multiply-accumulate subinstruction comprising generating at least one result value by multiplying a respective first value by a respective second value, and adding the at least one result value to an accumulator in an output register of the processor.