# US 2025/0165183 A1 · Memory controller and memory system including the same

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- Number: US 2025/0165183 A1
- Document ID: US20250165183A1
- Status: Published application
- Kind: A1
- Application number: 18/594,753
- Filed: 2024-03-04
- Published: 2025-05-22
- Earliest claimed: 2023-11-20
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Jihwan KIM; Young Ook SONG
- Web page: https://patentgrep.com/patent/US20250165183A1

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 13/1668: {Details of memory controller}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration}
- G06F 3/0673: {Single storage device}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory controller includes a response buffer configured to store responses provided from a memory device; a congestion monitoring circuit configured to monitor a congestion degree at an egress port of the memory controller; a priority control circuit configured to adjust a priority of commands to process second commands corresponding to an internal operation prior to first commands corresponding to a host-requested operation, based on the congestion degree at the egress port and a fill-level of the response buffer; and a command generation circuit configured to schedule the first commands and the second commands according to the priority and output the scheduled commands to the memory device.

## Claims

### Claim 1

A memory controller comprising:
a response buffer configured to store responses provided from a memory device;
a congestion monitoring circuit configured to monitor a congestion degree at an egress port of the memory controller;
a priority control circuit configured to adjust a priority of commands to process second commands corresponding to an internal operation prior to first commands corresponding to a host-requested operation, based on the congestion degree at the egress port and a fill-level of the response buffer; and
a command generation circuit configured to schedule the first commands and the second commands according to the priority and output the scheduled commands to the memory device.

### Claim 2 (depends on 1)

The memory controller of claim 1,
wherein the first commands include commands for performing an operation requested from a host device, and
wherein the second commands include commands for performing the internal operation that is not requested from the host device.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein the second commands include at least one of a write-queue flush command, a refresh command or a scrubbing command.

### Claim 4 (depends on 1)

The memory controller of claim 1,
wherein the congestion monitoring circuit is configured to determine an average congestion rate by tracking the congestion degree at the egress port for each monitoring section, and
wherein the priority control circuit is configured to determine a throughput based on the average congestion rate, determine a time window according to the fill-level of the response buffer and the throughput, and adjust the priority to process the second commands prior to the first commands by increasing the priority of the second commands according to a result of comparing the time window with execution times for the second commands.

### Claim 5 (depends on 4)

The memory controller of claim 4, wherein the priority control circuit is configured to determine the throughput based on the average congestion rate according to [Equation 1] below:
Throughput=maximum throughput*(1−average congestion rate). [Equation 1]

### Claim 6 (depends on 4)

The memory controller of claim 4,
wherein the priority control circuit is configured to:
align the execution times for the second commands in a descending order; and
sequentially compare the aligned execution times with the time window to increase the priority of a second command with a certain execution time less than the time window, or to maintain the priority of the second commands without increasing the priority when the execution time having a shortest time is equal to or greater than the time window.

### Claim 7 (depends on 4)

The memory controller of claim 4,
wherein the priority control circuit includes a look-up table having a plurality of fields obtained by combining two or more execution times for the second commands, and
wherein the priority control circuit is configured to increase the priority of the second commands stored in a field corresponding to the time window.

### Claim 8 (depends on 1)

The memory controller of claim 1,
wherein the response buffer is configured to transmit a response and a valid signal indicating that the response is valid, in response to a ready signal, and
wherein the congestion monitoring circuit is configured to determine an average congestion rate corresponding to the congestion degree at the egress port, by sampling cases in which a back-pressured condition has occurred for each monitoring section based on the ready signal and the valid signal.

### Claim 9 (depends on 8)

The memory controller of claim 8, wherein the congestion monitoring circuit includes:
a back-pressured history buffer configured to store a plurality of sampling signals obtained by sampling the ready signal and the valid signal at preset sampling intervals; and
an average calculator configured to generate a back-pressured count value by counting a number of sampling signals that satisfy the back-pressured condition, among the sampling signals, and generate the average congestion rate by tracking the back-pressured count value for each monitoring section.

### Claim 10 (depends on 9)

The memory controller of claim 9, wherein the average calculator is configured to determine that a sampling signal sampled when the ready signal is deactivated and the valid signal is activated, satisfies the back-pressured condition.

### Claim 11 (depends on 1)

The memory controller of claim 1, wherein the priority control circuit includes:
a window determination circuit configured to determine a throughput based on the congestion degree at the egress port, and determine a time window according to a ratio of the fill-level of the response buffer and the throughput; and
a scheduling control circuit configured to increase the priority of the second commands according to a result of comparing the time window with execution times for the second commands.

### Claim 12 (depends on 1)

The memory controller of claim 1, wherein the command generation circuit includes:
a first command generator configured to generate the first commands in response to a request from a host device;
a second command generator configured to generate the second commands corresponding to the internal operation regardless of the request from the host device, based on the priority;
a request queue configured to store the first commands and the second commands; and
an output control circuit configured to schedule the first commands and the second commands stored in the request queue, according to the priority.

### Claim 13 (depends on 1)

The memory controller of claim 1, further comprising:
a response counter configured to generate the fill-level by counting a number of valid responses stored in the response buffer; and
a transmitter configured to provide a ready signal to the response buffer and provide a response signal to a host device through the egress port, according to a valid signal provided from the response buffer.

### Claim 14

A memory system comprising:
a memory device; and
a memory controller configured to schedule second commands corresponding to an internal operation to be processed prior to first command corresponding to a host-requested operation, according to a congestion degree at an egress port of the memory system and a fill-level of a response buffer configured to store responses provided from the memory device.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein the memory controller is configured to:
store a plurality of sampling signals obtained by sampling a ready signal and a valid signal, which are input to and output from the response buffer, at preset sampling intervals;
generate a back-pressured count value by counting a number of sampling signals that satisfy a back-pressured condition, among the sampling signals, and
generate an average congestion rate corresponding to the congestion degree at the egress port, by tracking the back-pressured count value for each monitoring section.

### Claim 16 (depends on 14)

The memory system of claim 14, wherein the memory controller is configured to:
determine an average congestion rate by tracking the congestion degree at the egress port,
determine a throughput based on the average congestion rate,
determine a time window according to a ratio of the fill-level of the response buffer and the throughput, and
adjust a priority of the second commands by increasing the priority according to a result of comparing the time window with execution times for the second commands.

### Claim 17

An operating method of a memory controller, the operating method comprising:
determining a throughput based a congestion degree at an egress port of the memory controller;
determining a time window according to a fill-level of a response buffer that stores responses provided from a memory device and the throughput; and
scheduling second commands corresponding to an internal operation and first command corresponding to a host-requested operation, while adjusting a priority of the second commands according to a result of comparing the time window with execution times for the second commands.

### Claim 18 (depends on 17)

The operating method of claim 17, further comprising:
storing a plurality of sampling signals obtained by sampling a ready signal and a valid signal, which are input to and output from the response buffer, at preset sampling intervals;
generating a back-pressured count value by counting a number of sampling signals that satisfy the back-pressured condition, among the sampling signals; and
generating an average congestion rate corresponding to the congestion degree at the egress port, by tracking the back-pressured count value for each monitoring section.

### Claim 19 (depends on 17)

The operating method of claim 17, wherein the determining the time window includes:
increasing a width of the time window in accordance with a determination that the fill-level is greater and the throughput is lower; and
decreasing the time window in accordance with a determination that the fill-level is lower and the throughput is greater.

### Claim 20 (depends on 17)

The operating method of claim 17, wherein the adjusting a priority of the second commands includes:
aligning the execution times for the second commands in a descending order; and
sequentially comparing the aligned execution times with the time window to increase the priority of a second command with a certain execution time in accordance with a determination that the certain execution time is less than the time window, or to maintain the priority of the second commands without increasing the priority in accordance with a determination that the execution time having a shortest time is equal to or greater than the time window.