# US 2025/0165147 A1 · Methods, devices and systems for serial bus transactions with selectable data transaction sizes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0165147 A1 - Document ID: US20250165147A1 - Status: Published application - Kind: A1 - Application number: 18/678,193 - Filed: 2024-05-30 - Published: 2025-05-22 - Earliest claimed: 2023-11-22 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies LLC - Inventors: Avi AVANINDRA - Web page: https://patentgrep.com/patent/US20250165147A1 ## CPC - G06F 3/061: {Improving I/O performance} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method can include receiving, at a serial input/output (IO) of a memory device, at least command values, address values and metadata that includes an encoded length value in synchronism with a serial clock. From at least the command, address and encoded length values, a memory access operation, a memory array location, and one of a plurality of different data length values (LEN) corresponding to the memory access operation can be determined. At least data having a length corresponding to the one of the plurality of different LEN can be transferred at the serial IO in synchronism with the serial clock during execution of the memory access operation. Corresponding devices and systems are also disclosed. ## Claims ### Claim 1 A method, comprising: receiving, at a serial input/output (IO) of a memory device, at least command values, address values and metadata that includes an encoded length value in synchronism with a serial clock; determining from at least the command, address and encoded length values a memory access operation, a memory array location, and one of a plurality of different data length values (LEN) corresponding to the memory access operation; and transferring at least data having a length corresponding to the one of the plurality of different LEN at the serial IO in synchronism with the serial clock during execution of the memory access operation. ### Claim 2 (depends on 1) The method of claim 1, wherein: receiving the at least command values, address values and metadata includes receiving command bits in synchronism with the serial clock, receiving address bits in synchronism with the serial clock after the command bits, and receiving LEN bits in synchronism with the serial clock after the address bits. ### Claim 3 (depends on 1) The method of claim 1, wherein: receiving the at least command values, address values and metadata includes receiving a first set of command bits in synchronism with the serial clock, receiving a second set of command bits and LEN bits in synchronism with the serial clock after the first set, and receiving address bits in synchronism with the serial clock after the second set. ### Claim 4 (depends on 1) The method of claim 1, wherein: receiving the at least command values, address values and metadata includes receiving command bits in synchronism with the serial clock, receiving a first set of address bits in synchronism with the serial clock after the command bits, and receiving a second set of address bits and LEN bits in synchronism with the serial clock after the first set. ### Claim 5 (depends on 1) The method of claim 1, wherein the plurality of different data length values are multiples of X, wherein X is an integer. ### Claim 6 (depends on 1) The method of claim 1, wherein: determining that the memory access operation is a read operation; and transferring at least the data having the length corresponding to the one of the plurality of LEN comprises transferring read data of length LEN that is stored at an address corresponding to address values from the memory device at the serial IO. ### Claim 7 (depends on 1) The method of claim 1, wherein: determining that the memory access operation is an authenticated read operation; and transferring at least the data having the length corresponding to the one of the plurality of LEN comprises transferring read data of length LEN stored at an address corresponding to the address values followed by authentication data for authenticating the read data from the memory device at the serial IO. ### Claim 8 (depends on 1) The method of claim 1, wherein: determining that the memory access operation is a program or write operation; and transferring at least the data having the length corresponding to the one of the plurality of LEN comprises receiving program or write data of length LEN at the serial IO of the memory device. ### Claim 9 (depends on 1) The method of claim 1, wherein: determining that the memory access operation is an authenticated program or write operation; and transferring at least the data having the length corresponding to the one of the plurality of LEN comprises receiving program or write data of length LEN followed by authentication data at the serial IO of the memory device, the authentication data for authenticating at least the write or program data. ### Claim 10 (depends on 1) The method of claim 1, further including: by operation of a host device determining LEN for memory access operations, and in response to a request to access a memory space corresponding to the memory device, transmitting at least the command values, address values and metadata that includes the encoded length value to the serial IO in synchronism with the serial clock. ### Claim 11 A device, comprising: a memory cell array; decoder circuits configured to determine, a memory access operation from command values, a memory cell array location from address values, and one of a plurality of different data length values (LEN) from an encoded data length value included in metadata; control circuits configured to access the memory cell array location according to the memory access operation; and input/output (IO) circuits that include a serial clock input configured to receive a serial clock, and at least one serial IO configured to receive command values, address values, and the metadata in synchronism with the serial clock, and transfer at least data of the length LEN. ### Claim 12 (depends on 11) The device of claim 11, wherein the memory cell array comprises nonvolatile memory cells. ### Claim 13 (depends on 11) The device of claim 11, wherein the serial clock input and at least one serial IO are compatible with at least one Serial Peripheral Interface (SPI) standard. ### Claim 14 (depends on 11) The device of claim 11, wherein: the IO circuits are configured to receive command data bits in synchronism with the serial clock, receive address data bits in synchronism with the serial clock after the command bits, and receive encoded LEN bits in synchronism with the serial clock after the address bits. ### Claim 15 (depends on 11) The device of claim 11, wherein: the IO circuits are configured to receive a first set of command data bits in synchronism with the serial clock, receive a second set of command data bits and encoded LEN bits in synchronism with the serial clock after the first set, and receive address data bits in synchronism with the serial clock after the second set. ### Claim 16 (depends on 11) The device of claim 11, wherein: the IO circuits are configured to receive command data bits in synchronism with the serial clock, receive a first set of address data bits in synchronism with the serial clock after the command bits, and receive a second set of address bits and encoded LEN bits in synchronism with the serial clock after the first set. ### Claim 17 A system, comprising: a memory device that includes a memory cell array, control circuits configured to determine a memory access operation and location from command and address values, determine one of a plurality of data length values (LEN) from encoded data length values included in metadata, access the memory cell array location according to the memory access operation, and input/output (IO) circuits configured to receive command values, address values, and the metadata at a serial IO in synchronism with the serial clock, and transfer at least data of the length LEN; and a serial bus coupled to at least the IO circuits. ### Claim 18 (depends on 17) The system of claim 17, wherein: the IO circuits are configured to receive command values, address values, and encoded extended length values in a format selected from the group of: receiving command bits, followed by address bits followed by encoded extended length bits, and receiving command bits, followed by encoded length bits, followed by address bits. ### Claim 19 (depends on 17) The system of claim 17, further including: a host device that includes command address generator circuits configured to generate a first command value, a first address value and metadata that includes an encoded length value in an authenticated read operation, authentication circuits configured to authenticate at least read data with corresponding authentication data, host IO circuits coupled to the serial bus and configured to transmit the first command value, first address value, and the metadata at a host serial IO in synchronism with the serial clock, and receive read data of the length LEN and corresponding authentication data. ### Claim 20 (depends on 19) The system of claim 19, further including: the memory device includes a memory cell array comprising nonvolatile memory cells configured to store code; and the host device that includes processor circuits configured to execute the code directly from the memory device with authenticated read operations.