# US 2025/0159997 A1 · Enlarged bottom contact area in stacked transistors

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- Number: US 2025/0159997 A1
- Document ID: US20250159997A1
- Status: Published application
- Kind: A1
- Application number: 18/509,382
- Filed: 2023-11-15
- Published: 2025-05-15
- Earliest claimed: 2023-11-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Jay William Strane; Ruilong Xie; Albert M. Chu; Junli Wang
- Web page: https://patentgrep.com/patent/US20250159997A1

## CPC

- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor on a substrate; a second transistor on top of the first transistor; and a source/drain (S/D) contact contacting a first S/D region of the first transistor, where the S/D contact has a horizontal portion and a vertical portion, the horizontal portion extending from a sidewall of the vertical portion and a portion of the horizontal portion being vertically between the first S/D region of the first transistor and a second S/D region of the second transistor. A method of forming the same is also provided.

## Claims

### Claim 1

A semiconductor structure comprising:
a first transistor on a substrate;
a second transistor on top of the first transistor; and
a source/drain (S/D) contact contacting a first S/D region of the first transistor,
wherein the S/D contact has a horizontal portion and a vertical portion, the horizontal portion extending from a sidewall of the vertical portion and a portion of the horizontal portion being vertically between the first S/D region of the first transistor and a second S/D region of the second transistor.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a portion of the first S/D region of the first transistor is vertically outside the second S/D region of the second transistor.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein a bottom surface of the vertical portion of the S/D contact is in direct contact with the portion of the first S/D region of the first transistor and is below the horizontal portion of the S/D contact.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein a portion of the sidewall of the vertical portion of the S/D contact is in direct contact with the portion of the first S/D region of the first transistor and is below the horizontal portion of the S/D contact.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the horizontal portion of the S/D contact is horizontally in contact with a dummy sheet, the dummy sheet being directly on top of the first S/D region of the first transistor.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the horizontal portion of the S/D contact and the dummy sheet have a substantially same thickness and are substantially coplanar.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the first transistor is a first nanosheet transistor having a first set of nanosheets of a first width, the second transistor is a second nanosheet transistor having a second set of nanosheets of a second width, and the second width is narrower than the first width.

### Claim 8

A method of forming a semiconductor structure comprising:
forming a first source/drain (S/D) region of a first transistor on a substrate;
forming a sacrificial sheet directly on top of the first S/D region of the first transistor;
forming a second S/D region of a second transistor, the second S/D region being on top of the first S/D region such that a portion of the first S/D region of the first transistor being vertically outside the second S/D region of the second transistor;
depositing a dielectric layer covering the first and the second S/D region;
creating a vertical opening in the dielectric layer, the vertical opening exposing the portion of the first S/D region;
selectively removing at least a portion of the sacrificial sheet to create a horizontal opening directly above the first S/D region of the first transistor; and
forming a S/D contact, the S/D contact having a horizontal portion in the horizontal opening and a vertical portion in the vertical opening.

### Claim 9 (depends on 8)

The method of claim 8, wherein the vertical opening extends through the sacrificial sheet to expose a sidewall thereof.

### Claim 10 (depends on 9)

The method of claim 9, wherein selectively removing the at least a portion of the sacrificial sheet comprises selectively etching the sacrificial sheet through the sidewall exposed by the vertical opening.

### Claim 11 (depends on 9)

The method of claim 9, wherein selectively removing the at least a portion of the sacrificial sheet comprises selectively etching the sacrificial sheet to create the horizontal opening where at least a portion of the horizontal opening is vertically between the first S/D region of the first transistor and the second S/D region of the second transistor.

### Claim 12 (depends on 11)

The method of claim 11, wherein selectively etching the sacrificial sheet causes a portion of the sacrificial sheet to remain above the first S/D region of the first transistor as a dummy sheet.

### Claim 13 (depends on 11)

The method of claim 11, wherein selectively etching the sacrificial sheet causes the sacrificial sheet above the first S/D region of the first transistor being entirely removed.

### Claim 14 (depends on 8)

The method of claim 8, wherein forming the S/D contact comprises depositing a conductive material in the horizontal opening and the vertical portion to form the horizontal portion and the vertical portion of the S/D contact.

### Claim 15

A semiconductor structure comprising:
a first nanosheet transistor on a substrate;
a second nanosheet transistor on top of the first nanosheet transistor; and
a source/drain (S/D) contact contacting a first S/D region of the first nanosheet transistor,
wherein the S/D contact has a horizontal portion and a vertical portion, the horizontal portion extending from a sidewall of the vertical portion and covering a top surface of the first S/D region of the first nanosheet transistor.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the first nanosheet transistor has a first set of nanosheets of a first width and the second nanosheet transistor has a second set of nanosheets of a second width with the second width being narrower than the first width, and wherein and a portion of the first S/D region of the first nanosheet transistor is vertically outside the second S/D region of the second nanosheet transistor.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein a bottom surface of the vertical portion of the S/D contact is in direct contact with the portion of the first S/D region of the first nanosheet transistor and is below the horizontal portion of the S/D contact.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein a portion of the sidewall of the vertical portion of the S/D contact is in direct contact with the portion of the first S/D region of the first nanosheet transistor and is below the horizontal portion of the S/D contact.

### Claim 19 (depends on 15)

The semiconductor structure of claim 15, wherein at least a portion of the horizontal portion of the S/D contact is vertically between the first S/D region of the first nanosheet transistor and the second S/D region of the second nanosheet transistor, and the horizontal portion of the S/D contact is horizontally in contact with a dummy sheet, the dummy sheet being directly on top of the first S/D region of the first nanosheet transistor.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein the horizontal portion of the S/D contact and the dummy sheet have a substantially same thickness and are substantially coplanar.