# US 2025/0159986 A1 · Cut-mask patterning to remove corner- rounding of active regions of semiconductor device

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- Number: US 2025/0159986 A1
- Document ID: US20250159986A1
- Status: Published application
- Kind: A1
- Application number: 18/639,141
- Filed: 2024-04-18
- Published: 2025-05-15
- Earliest claimed: 2023-11-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kang-min JUNG; Kang-ill SEO
- Web page: https://patentgrep.com/patent/US20250159986A1

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- G03F 1/70: Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/502: {characterised by the stacked channels}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Provided is a semiconductor device which includes: a 1st active region extended in a 1st direction and including: a 1st out-corner edge at which a width of the 1st active region in a 2nd direction gradually changes along the 1st direction; and a 1st in-corner edge at which the width of the 1st active region less gradually changes along the 1st direction than at the 1st out-corner edge; and a gate structure extended in the 2nd direction and overlapping the 1st out-corner edge in a 3rd direction, wherein the 1st direction horizontally intersects the 2nd direction, and the 3rd direction vertically intersects the 1st direction and the 2nd direction.

## Claims

### Claim 1

A semiconductor device comprising:
a 1st active region extended in a 1st direction and comprising:
a 1st out-corner edge at which a width of the 1st active region in a 2nd direction gradually changes along the 1st direction; and
a 1st in-corner edge at which the width of the 1st active region less gradually changes along the 1st direction than at the 1st out-corner edge; and
a gate structure extended in the 2nd direction and overlapping the 1st out-corner edge in a 3rd direction,
wherein the 1st direction horizontally intersects the 2nd direction, and the 3rd direction vertically intersects the 1st direction and the 2nd direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the 1st active region comprises;
a 1st source/drain region;
a 2nd source/drain region; and
a 1st channel structure between the 1st source/drain region and the 2nd source/drain region, and overlapped by the gate structure in the 3rd direction,
wherein the 1st out-corner edge overlapped by the gate structure in the 3rd direction is included in the 1st channel structure.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the 1st source/drain region has a 1st width in the 2nd direction, and the 2nd source/drain region has a 2nd width in the 2nd direction, different from the 1st width.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a 2nd active region extended in the 1st direction, above the 1st active region, and comprising:
a 2nd out-corner edge at which a width of the 2nd active region in the 2nd direction gradually changes along the 1st direction; and
a 2nd in-corner edge at which the width of the 2nd active region less gradually changes along the 1st direction than at the 2nd out-corner edge,
wherein the gate structure overlaps the 2nd out-corner edge in the 3rd direction.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the width of the 1st active region is greater than the width of the 2nd active region.

### Claim at position 6

6-7. (canceled)

### Claim 8 (depends on 4)

The semiconductor device of claim 4, wherein the 1st active region comprises;
a 1st source/drain region;
a 2nd source/drain region;
a 1st channel structure between the 1st source/drain region and the 2nd source/drain region, and overlapped by the gate structure in the 3rd direction;
a 3rd source/drain region above the 1st source/drain region in the 3rd direction;
a 4th source/drain region above the 2nd source/drain region in the 3rd direction; and
a 2nd channel structure between the 3rd source/drain region and the 4th source/drain region, and overlapped by the gate structure in the 3rd direction,
wherein the 1st out-corner edge is included in the 1st channel structure, and
wherein the 2nd out-corner edge is included in the 2nd channel structure.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the 1st source/drain region has a 1st width in the 2nd direction, and the 2nd source/drain region has a 2nd width in the 2nd direction, different from the 1st width, and
wherein the 3rd source/drain region has a 3rd width in the 2nd direction, and the 4th source/drain region has a 4th width in the 2nd direction, different from the 3rd width.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the 1st active region comprises:
a 1st region at a 1st side of the 1st out-corner edge opposite to the 1st in-corner edge, the 1st region having a 1st width in the 2nd direction; and
a 2nd region at a 2nd side of the 1st in-corner edge opposite to the 1st out-corner edge, the 2nd region having a 2nd width in the 2nd direction,
where the 1st width is uniform along the 1st direction, and the 2nd width is uniform in the 1st direction, and
wherein the 1st width is different from the 2nd width.

### Claim 11

(canceled)

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the 2nd active region comprises:
a 3rd region at the 1st side of the 2nd out-corner edge opposite to the 2nd in-corner edge, the 3rd region having a 3rd width in the 2nd direction; and
a 4th region at the 2nd side of the 2nd in-corner edge opposite to the 2nd out-corner edge, the 4th region having a 4th width in the 2nd direction,
where the 3rd width is uniform along the 1st direction, and the 4th width is uniform along the 1st direction, and
wherein the 3rd width is different from the 4th width.

### Claim at position 12

13-14. (canceled)

### Claim 15

A semiconductor device comprising:
a 1st channel structure;
a 1st source/drain region connected to the 1st channel structure;
a 2nd source/drain region connected to the 1st channel structure; and
a gate structure configured to control current flow between the 1st source/drain region and the 2nd source/drain region through the 1st channel structure,
wherein a width of the 1st channel structure in a 2nd direction gradually changes along a 1st direction which intersects the 2nd direction.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate structure overlaps the 1st channel structure in a 3rd direction which intersects the 1st direction and the 2nd direction.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a width of the 1st source/drain in a 2nd direction is greater than a width of the 2nd source/drain region in the 2nd direction.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the 1st source/drain region is included in a 1st cell of the semiconductor device, and the 2nd source/drain region is included in a 2nd cell of the semiconductor device.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further comprising:
a 2nd channel structure above the 1st channel structure in the 3rd direction
a 3rd source/drain region above the 1st source/drain region in 3rd direction and connected to the 2nd channel structure;
a 4th source/drain region above the 2nd source/drain region in the 3rd direction and connected to the 2nd channel structure; and
wherein the gate structure is configured to control current flow between the 3rd source/drain region and the 4th source/drain region through the 2nd channel structure,
wherein a width of the 2nd channel structure in the 2nd direction gradually varies along the 1st direction.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the gate structure overlaps the 2nd channel structure in the 3rd direction.

### Claim 21 (depends on 19)

The semiconductor device of claim 19, wherein a width of the 3rd source/drain in the 2nd direction is greater than a width of the 4th source/drain region in the 2nd direction.

### Claim at position 20

22-23. (canceled)

### Claim 24

A semiconductor device comprising:
a 1st cell comprising a 1st active region;
a 2nd cell comprising a 2nd active region, the 2nd cell being adjacent to the 1st cell in a 1st direction, and the 2nd active region being aligned with the 1st active region in the 1st direction; and
a gate structure extended in the 2nd direction across at least one of the 1st active region and the 2nd active region,
wherein the 1st active region has a 1st width, and the 2nd active region has a 2nd width smaller than the 1st width in the 2nd direction,
wherein the 1st active region comprises a 1st out-corner edge, at which the 1st width gradually changes, the 1st out-corner edge being overlapped by the gate structure in a 3rd direction which intersects the 1st direction and the 2nd direction, and
wherein the 2nd active region comprises a 1st in-corner edge at which the 2nd width less gradually changes than at the 1st out-corner edge.

### Claim 25

(canceled)

### Claim 26 (depends on 24)

The semiconductor device of claim 24, further comprising a 1st channel structure connecting the 1st active region and the 2nd active region,
wherein the 1st channel structure is overlapped by the gate structure in the 3rd direction and comprises the 1st out-corner edge.

### Claim 27 (depends on 24)

The semiconductor device of claim 24, wherein the 1st cell further comprises a 3rd active region above the 1st active region in the 3rd direction, and the 2nd cell further comprises a 4th active region above the 2nd active region,
wherein the 4th active region is aligned with the 3rd active region in the 1st direction,
wherein the 3rd active region has a 3rd width, and the 4th active region has a 4th width smaller than the 3rd width in the 2nd direction,
wherein the 3rd active region comprises a 2nd out-corner edge, at which the 3rd width gradually changes, the 3rd out-corner edge being overlapped by the gate structure in the 3rd direction, and
wherein the 4th active region comprises a 2nd in-corner edge at which the 4th width less gradually changes than at the 2nd out-corner edge.

### Claim 28

(canceled)

### Claim 29 (depends on 27)

The semiconductor device of claim 27, further comprising a 2nd channel structure connecting the 3rd active region and the 4th active region,
wherein the 2nd channel structure is overlapped by the gate structure in the 3rd direction and comprises the 2nd out-corner edge.

### Claim at position 27

30-40. (canceled)