# US 2025/0159979 A1 · Semiconductor device including contact structures having different dimensions

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- Number: US 2025/0159979 A1
- Document ID: US20250159979A1
- Status: Published application
- Kind: A1
- Application number: 18/606,001
- Filed: 2024-03-15
- Published: 2025-05-15
- Earliest claimed: 2023-11-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Panjae PARK; Jintae KIM; Hyojong SHIN
- Web page: https://patentgrep.com/patent/US20250159979A1

## CPC

- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/01: {Manufacture or treatment}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Provided is a semiconductor device which includes: a 1st channel structure; a 1st source/drain region and a 2nd source/drain region connected through the 1st channel structure in a 1st direction; a 1st gate structure on the 1st channel structure; a 1st contact structure on the 1st source/drain region and connecting the 1st source/drain region to a voltage source; and a 2nd contact structure on the 2nd source/drain region and connecting the 2nd source/drain region to another circuit element other than a voltage source, wherein a 1st contact area between the 1st contact structure and the 1st source/drain region is greater than a 2nd contact area between the 2nd contact structure and the 2nd source/drain region.

## Claims

### Claim 1

A semiconductor device comprising:
a 1st channel structure;
a 1st source/drain region and a 2nd source/drain region connected through the 1st channel structure in a 1st direction;
a 1st gate structure on the 1st channel structure;
a 1st contact structure on the 1st source/drain region and connecting the 1st source/drain region to a voltage source; and
a 2nd contact structure on the 2nd source/drain region and connecting the 2nd source/drain region to another circuit element other than a voltage source,
wherein a 1st contact area between the 1st contact structure and the 1st source/drain region is greater than a 2nd contact area between the 2nd contact structure and the 2nd source/drain region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein one or more of a 1st contact length in the 1st direction, a 1st contact width in a 2nd direction, and a 1st contact height in a 3rd direction between the 1st contact structure and the 1st source/drain region is greater than one or more of a 2nd contact length in the 1st direction, a 2nd contact width in a 2nd direction, and a 2nd contact height in a 3rd direction between the 2nd contact structure and the 2nd source/drain region, respectively.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a 1st contact length in the 1st direction between the 1st contact structure and the 1st source/drain region is greater than a 2nd contact length in the 1st direction between the 2nd contact structure and the 2nd source/drain region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein an isolation structure is disposed at a side surface of each of the 1st contact structure and the 2nd contact structure.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein at least one gate spacer is disposed to contact at least a portion of a side surface of each of the 1st contact structure and the 2nd contact structure.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the at least a portion of a side surface of each of the 1st contact structure and the 2nd contact structure is a lower side surface of each of the 1st contact structure and the 2nd contact structure close to each of the 1st source/drain region and the 2nd source/drain region.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein a length of the at least one gate spacer contacting the side surface of the 1st contact structure is smaller than a length of the at least one gate spacer contacting the side surface of the 2nd contact structure.

### Claim 8 (depends on 3)

The semiconductor device of claim 3, further comprising:
a 2nd gate structure at a side of the 1st gate structure in the 1st direction;
a 3rd gate structure at an opposite side of the 1st gate structure in the 1st direction;
wherein the 1st contact length is defined by a distance between a gate spacer on a side surface of the 2nd gate structure and an extra gate spacer on a gate spacer on a side surface of the 1st gate structure, and
wherein the 2nd contact length is defined by a distance between an extra gate spacer on a gate spacer on another side surface of the 1st gate structure and an extra gate spacer on a gate spacer on a side surface of the 3rd gate structure.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a 1st distance between the 1st contact structure and the 1st gate structure is smaller than a 2nd distance between the 2nd contact structure and the 1st gate structure.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a 2nd channel structure; and
a 3rd source/drain region and a 4th source/drain region respectively overlapping the 1st source/drain region and the 2nd source/drain region in a 3rd direction intersecting the 1st direction, the 3rd source/drain region and the 4th source/drain region being connected through the 2nd channel structure in the 1st direction;
a 4th contact structure on the 4th source/drain region connecting the 4th source/drain region to the 2nd source/drain region through the 2nd contact structure.

### Claim 11 (depends on 10)

The 3D-stacked semiconductor device of claim 10, further comprising:
a 3rd contact structure on the 3rd source/drain region connecting the 3rd source/drain region to another voltage source.

### Claim 12

A semiconductor device comprising:
a 1st channel structure;
a 1st source/drain region and a 2nd source/drain region connected through the 1st channel structure in a 1st direction;
a 1st gate structure on the 1st channel structure;
a 1st contact structure on the 1st source/drain region and connecting the 1st source/drain region to a voltage source; and
a 2nd contact structure on the 2nd source/drain region and connecting the 2nd source/drain region to another circuit element other than a voltage source,
wherein a 1st contact length between the 1st contact structure and the 1st source/drain region is greater than a 2nd contact length between the 2nd contact structure and the 2nd source/drain region in the 1st direction.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a 1st distance between the 1st contact structure and the 1st gate structure is smaller than a 2nd distance between the 2nd contact structure and the 1st gate structure.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein an isolation structure is disposed at a side surface of each of the 1st contact structure and the 2nd contact structure.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein at least one gate spacer is disposed to contact at least a portion of a side surface of each of the 1st contact structure and the 2nd contact structure.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, further comprising:
a 2nd channel structure; and
a 3rd source/drain region and a 4th source/drain region respectively overlapping the 1st source/drain region and the 2nd source/drain region in a 3rd direction intersecting the 1st direction, the 3rd source/drain region and the 4th source/drain region being connected through the 2nd channel structure in the 1st direction;
a 4th contact structure on the 4th source/drain region connecting the 4th source/drain region to the 2nd source/drain region through the 2nd contact structure.

### Claim 17

A semiconductor device comprising:
a 1st channel structure; and
a 1st source/drain region and a 2nd source/drain region connected through the 1st channel structure in a 1st direction;
a 1st gate structure on the 1st channel structure;
a 1st contact structure on the 1st source/drain region and connecting the 1st source/drain region to a voltage source; and
a 2nd contact structure on the 2nd source/drain region and connecting the 2nd source/drain region to another circuit element other than one or more voltage sources,
wherein a 1st contact height between the 1st contact structure and the 1st source/drain region is greater than a 2nd contact height between the 2nd contact structure and the 2nd source/drain region in a 3rd direction.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a 1st distance between the 1st contact structure and the 1st gate structure is smaller than a 2nd distance between the 2nd contact structure and the 1st gate structure.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein a 1st distance between the 1st contact structure and the 1st gate structure is smaller than a 2nd distance between the 2nd contact structure and the 1st gate structure.

### Claim at position 20

20-24. (canceled)