# US 2025/0159944 A1 · Methods of forming semiconductor devices having liners

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- Number: US 2025/0159944 A1
- Document ID: US20250159944A1
- Status: Published application
- Kind: A1
- Application number: 19/022,308
- Filed: 2025-01-15
- Published: 2025-05-15
- Earliest claimed: 2013-06-19
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Christopher J. Larsen; David A. Daycock; Kunal Shrotri
- Web page: https://patentgrep.com/patent/US20250159944A1

## CPC

- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B 41/30: characterised by the memory core region
- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- H10D 30/68: Floating-gate IGFETs
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6529: {by exposure to a gas or vapour}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a control gate material adjacent to a stack of materials, the control gate material comprising a metallic material;
patterning the control gate material to form features extending from the stack of materials;
forming a liner material comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride on the control gate material, the liner material extending substantially continuously on the features;
exposing the liner material to a gas mixture comprising oxygen radicals, hydrogen radicals, or a combination of oxygen radicals and hydrogen radicals to form a densified liner; and
removing a portion of the stack of materials underlying the control gate material without removing the control gate material to form an array of memory cells.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming a control gate material adjacent to a stack of materials comprises forming a doped conductive material adjacent to the stack of materials and the metallic material adjacent to the doped conductive material.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming a doped conductive material adjacent to the stack of materials and the metallic material adjacent to the doped conductive material comprises forming a doped conductive material comprising doped polysilicon adjacent to the stack of materials and the metallic material comprising tungsten adjacent to the doped conductive material.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming a liner material comprises forming the liner material over exposed surfaces of the control gate material.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the liner material over exposed surfaces of the control gate material comprises conformally forming the liner material on sidewalls of the control gate material and on an upper surface of the stack of materials.

### Claim 6 (depends on 1)

The method of claim 1, further comprising exposing the liner material to a temperature between about 600° C. and about 1200° C. while exposing the liner material to the gas mixture.

### Claim 7 (depends on 1)

The method of claim 1, further comprising exposing the liner material to a temperature between about 600° C. and about 1200° C. before exposing the liner material to the gas mixture.

### Claim 8

A method of forming a semiconductor device, the method comprising:
forming control gates comprising a conductive material adjacent to a stack of materials, the stack of materials comprising a tunnel dielectric material, a charge structure material, and a charge block material;
forming a liner material comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride directly on sidewalls of the control gates, the liner material exhibiting an initial density;
exposing the liner material to a radical oxidation treatment to form a densified liner, the densified liner exhibiting a density relatively greater than the initial density of the liner material; and
patterning the stack of materials to form memory cells comprising the tunnel dielectric material, the charge structure material, and the charge block material without patterning the control gates.

### Claim 9 (depends on 8)

The method of claim 8, wherein exposing the liner material to a radical oxidation treatment to form a densified liner comprises forming the densified liner at a thickness about equal to a thickness of the liner material.

### Claim 10 (depends on 8)

The method of claim 8, wherein exposing the liner material to a radical oxidation treatment to form a densified liner comprises forming the densified liner at a thickness relatively less than a thickness of the liner material.

### Claim 11 (depends on 8)

The method of claim 8, wherein patterning the stack of materials to form memory cells comprises removing portions of the stack of materials to form the memory cells comprising the tunnel dielectric material, the charge structure material, and the charge block material, sidewalls of the tunnel dielectric material, the charge structure material, and the charge block material sloped relative to the sidewalls of the control gates.

### Claim 12 (depends on 8)

The method of claim 8, wherein patterning the stack of materials to form memory cells comprising the tunnel dielectric material, the charge structure material, and the charge block material comprises removing a portion of the densified liner from sidewalls of the conductive material.

### Claim 13 (depends on 8)

The method of claim 8, wherein, after patterning the stack of materials, sidewalls of the control gates and an insulating material adjacent to the control gates are substantially aligned.

### Claim 14

A method of forming a semiconductor device, the method comprising:
forming a stack of materials adjacent to a base material, the stack of materials comprising a tunnel dielectric material, a charge trap material, a charge block material, a gate material, and a cap material;
removing a portion of the stack of materials to form features extending from the base material;
conformally forming a liner material on the features, the liner material comprising an oxide material, a nitride material, or an oxynitride material;
exposing the liner material to a gas mixture comprising oxygen radicals, hydrogen radicals, or a combination thereof to densify the liner material;
removing the densified liner material between adjacent features to expose an upper surface of the stack of materials; and
removing an additional portion of the stack of materials exposed between the adjacent features.

### Claim 15 (depends on 14)

The method of claim 14, wherein removing a portion of the stack of materials to form features extending from the base material comprises forming control gates extending from the base material.

### Claim 16 (depends on 14)

The method of claim 14, wherein removing the densified liner material between adjacent features comprises removing the densified liner material from the upper surface of the stack of materials while the densified liner material remains on sidewalls of the cap material and of the gate material.

### Claim 17 (depends on 14)

The method of claim 14, wherein removing an additional portion of the stack of materials exposed between the adjacent features comprises forming regions of the tunnel dielectric material, the charge trap material, and the charge block material exhibiting a greater width than a width of the features.

### Claim 18 (depends on 14)

The method of claim 14, further comprising removing a portion of the densified liner material from the features.

### Claim 19 (depends on 18)

The method of claim 18, wherein removing a portion of the densified liner material from the features comprises removing the portion of the densified liner material from the gate material.

### Claim 20 (depends on 18)

The method of claim 18, wherein removing a portion of the densified liner material from the features comprises removing the portion of the densified liner material from the gate material without substantially removing the densified liner material from the cap material.