# US 2025/0159933 A1 · Device performance diversification

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- Number: US 2025/0159933 A1
- Document ID: US20250159933A1
- Status: Published application
- Kind: A1
- Application number: 18/505,668
- Filed: 2023-11-09
- Published: 2025-05-15
- Earliest claimed: 2023-11-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shu-Wei Wang; Hsin Yang Hung; Wei-Xiang You; Jui-Chien Huang; Szuya Liao
- Web page: https://patentgrep.com/patent/US20250159933A1

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a first semiconductor layer over the substrate;
a second semiconductor layer over the first semiconductor layer and comprising a channel region sandwiched between a first source/drain region and a second source/drain region;
a first plurality of nanostructures disposed over the channel region;
a first leakage block layer disposed over the first source/drain region;
a second leakage block layer disposed over the second source/drain region;
a dielectric layer disposed on the first leakage block layer;
a first source/drain feature disposed on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures; and
a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures,
wherein the first leakage block layer and the second leakage block layer comprise an undoped semiconductor material.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first source/drain feature and the second source/drain feature comprise silicon germanium (SiGe) and a p-type dopant.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1,
wherein the substrate and the second semiconductor layer comprise silicon (Si),
wherein the first semiconductor layer comprises silicon germanium (SiGe).

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the first leakage block layer and the second leakage block layer comprise undoped germanium (Ge) or undoped silicon germanium (SiGe).

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer comprise silicon nitride.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a first gate structure wrapping around at least one of the first plurality of nanostructures;
a middle dielectric layer over the first plurality of nanostructures;
a second plurality of nanostructures over the middle dielectric layer; and
a second gate structure wrapping around at least one of the second plurality of nanostructures,
wherein a composition of the first gate structure is different from a composition of the second gate structure.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6,
wherein the first gate structure comprises titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), or nickel silicide (NiSi2),
wherein the second gate structure comprises titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicide nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), or titanium aluminum nitride (TiAlN).

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, further comprising:
a third source/drain feature disposed over the first source/drain feature; and
a fourth source/drain feature disposed over the second source/drain feature,
wherein the second plurality of nanostructures are sandwiched between and in contact with the third source/drain feature and the fourth source/drain feature.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the third source/drain feature and the fourth source/drain feature comprise silicon (Si) and an n-type dopant.

### Claim 10

A semiconductor structure, comprising:
a substrate;
a first fin and a second fin rising from the substrate and spaced apart from one another by an isolation feature;
a first leakage block layer over the first fin;
a second leakage block layer over the second fin;
first spacer features disposed along sidewalls of the first leakage block layer;
second spacer features disposed along sidewalls of the second leakage block layer;
a dielectric layer disposed over the first spacer features, the first leakage block layer and a portion of the isolation feature;
a first source/drain feature disposed over the dielectric layer; and
a second source/drain feature disposed over the second leakage block layer and the second spacer features,
wherein the first source/drain feature is spaced apart from the first leakage block layer and the first spacer features by the dielectric layer,
wherein the second source/drain feature is in direct contact with the second leakage block layer and the second spacer features.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the first source/drain feature and the second source/drain feature comprise silicon germanium (SiGe) and a p-type dopant.

### Claim 12 (depends on 10)

The semiconductor structure of claim 10, wherein the dielectric layer comprise silicon nitride.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10, wherein the first leakage block layer and the second leakage block layer comprise undoped germanium (Ge) or undoped silicon germanium (SiGe).

### Claim 14 (depends on 10)

The semiconductor structure of claim 10,
wherein each of the first fin and the second fin comprises:
a base portion rising from the substrate;
a middle portion formed of a first semiconductor material; and
a top portion formed of a second semiconductor material,
wherein the substrate and the top portion comprise silicon (Si),
wherein the middle portion comprises silicon germanium (SiGe).

### Claim 15 (depends on 10)

The semiconductor structure of claim 10, further comprising:
a contact etch stop layer (CESL) disposed over the dielectric layer, the first source/drain feature, the isolation feature, the second spacer features, and the second source/drain feature,
wherein the CESL is in direct contact with the dielectric layer, the first source/drain feature, the isolation feature, the second spacer features, and the second source/drain feature.

### Claim 16 (depends on 10)

The semiconductor structure of claim 10, wherein the CESL is spaced apart from the first spacer features by the dielectric layer.

### Claim 17

A method, comprising:
receiving a workpiece comprising:
a fin-shaped structure extending lengthwise along a direction, the fin-shaped structure comprising bottom sacrificial layers interleaved by bottom channel layers, a middle semiconductor layer over a topmost one of the bottom channel layers, and top sacrificial layers interleaved by top channel layers,
a dummy gate stack over a channel region of the fin-shaped structure, and
top gate spacers disposed along sidewalls of the dummy gate stack;
anisotropically etching a first source/drain region and a second source/drain region of the fin-shaped structure to form a first source/drain recess and a second source/drain recess, respectively, the first source/drain region and the second source/drain region sandwiching the channel region, sidewalls of the bottom channel layers and top channel layers being exposed in the first source/drain recess and the second source/drain recess;
forming a first leakage block layer over the first source/drain recess and a second leakage block layer over the second source/drain recess;
conformally depositing a sealing layer over dummy gate stack, the top gate spacers, the first leakage block layer, and the second leakage block layer;
selectively removing the sealing layer over the second leakage block layer to expose the second leakage block layer;
forming a first source/drain feature in contact with the sidewalls of the bottom channel layers and over the sealing layer; and
forming a second source/drain feature in contact with the sidewalls of the bottom channel layers and over the second leakage block layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
depositing a bottom contact etch stop layer (CESL) over the first source/drain feature and the second source/drain feature;
depositing a bottom interlayer dielectric layer (ILD) over the bottom CESL;
forming a third source/drain feature over the ILD and the first source/drain feature; and
forming a fourth source/drain feature over the ILD and the second source/drain feature.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first leakage block layer and the second leakage block layer comprise undoped semiconductor material.

### Claim 20 (depends on 17)

The method of claim 17, wherein the sealing layer comprises silicon nitride.