# US 2025/0159918 A1 · Gate isolation features

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- Number: US 2025/0159918 A1
- Document ID: US20250159918A1
- Status: Published application
- Kind: A1
- Application number: 18/505,632
- Filed: 2023-11-09
- Published: 2025-05-15
- Earliest claimed: 2023-11-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tzu-Chung Wang; Chih-Chang Hung
- Web page: https://patentgrep.com/patent/US20250159918A1

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Devices with isolated metal structures and methods of fabrication are provided. A method for isolating a metal gate includes forming a gate line over a semiconductor substrate; patterning a mask over the gate line, wherein an opening in the mask is located over a region of the gate line to be removed; performing an etching process through the opening to form a trench; and forming an isolation feature in the trench, wherein the isolation feature is selectively formed with no air gap, with a small air gap, or with a full air gap.

## Claims

### Claim 1

A method for isolating a metal gate, the method comprising:
forming a gate line over a semiconductor substrate;
patterning a mask over the gate line, wherein an opening in the mask is located over a region of the gate line to be removed;
performing an etching process through the opening to form a trench; and
forming an isolation feature in the trench, wherein the isolation feature is selectively formed with no air gap, with a small air gap, or with a full air gap.

### Claim 2 (depends on 1)

The method of claim 1, wherein the gate line is a dummy gate line, and wherein the method further comprises:
after forming the isolation feature in the trench, removing the dummy gate line to form a gate cavity; and
forming a metal gate structure in the gate cavity and adjacent to the isolation feature.

### Claim 3 (depends on 1)

The method of claim 1, wherein the gate line is a metal gate line, and wherein the method further comprises:
forming a dummy gate line over the semiconductor substrate;
forming an interlayer dielectric adjacent to the dummy gate line; and
removing the dummy gate line to form a gate cavity;
wherein forming the gate line over the semiconductor substrate comprises forming the metal gate line in the gate cavity.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
performing the etching process through the opening to form the trench comprises forming a V-shaped trench; and
forming the isolation feature in the trench comprises forming the isolation feature with no air gap.

### Claim 5 (depends on 1)

The method of claim 1, wherein:
performing the etching process through the opening to form the trench comprises forming a spear-shaped trench; and
forming the isolation feature in the trench comprises forming the isolation feature with a small air gap.

### Claim 6 (depends on 1)

The method of claim 1, wherein:
performing the etching process through the opening to form the trench comprises forming a carrot-shaped trench; and
forming the isolation feature in the trench comprises forming the isolation feature with a full air gap.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
forming the isolation feature in the trench comprises depositing a single layer of isolation material.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
forming the isolation feature in the trench comprises depositing multiple layer of isolation material to form a multi-layer isolation feature.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the isolation feature in the trench comprises performing a deposition process to deposit isolation material in the trench, and wherein the method further comprises controlling the etching process and the deposition process to form a selected air gap at a desired depth within the isolation feature.

### Claim 10

A method comprising:
designing a layout of an integrated circuit including a device comprising a first gate structure and a second gate structure separated by an isolation feature;
determining a desired device performance condition and/or a desired process yield condition;
selecting a structure of the isolation feature to provide the desired device performance condition, wherein the structure of the isolation feature comprises a selected shape; and
performing an integrated circuit fabrication process comprising:
forming a gate line over a semiconductor substrate;
performing an etching process to remove a portion of the gate line and form a trench with the selected shape; and
forming an isolation feature in the trench, wherein the isolation feature is selectively formed with no air gap, with a small air gap, or with a full air gap.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
the selected shape is a V-shape; and
forming the isolation feature in the trench comprises forming the isolation feature with no air gap.

### Claim 12 (depends on 10)

The method of claim 10, wherein:
the selected shape is a spear-shape; and
forming the isolation feature in the trench comprises forming the isolation feature with a small air gap.

### Claim 13 (depends on 10)

The method of claim 10, wherein:
the selected shape is a carrot-shape; and
forming the isolation feature in the trench comprises forming the isolation feature with a full air gap.

### Claim 14 (depends on 10)

The method of claim 10, wherein:
the selected shape is a carrot-shape; and
forming the isolation feature in the trench comprises forming the isolation feature with a full air gap.

### Claim 15 (depends on 10)

The method of claim 10, wherein forming the isolation feature in the trench comprises depositing multiple layers of isolation material or materials to form a multi-layer isolation feature.

### Claim 16 (depends on 10)

The method of claim 10, wherein:
the structure of the isolation feature comprises a selected depth of an air gap within the isolation feature; and
forming the isolation feature in the trench comprises forming the isolation feature with a small air gap or with a full air gap at the selected depth.

### Claim 17

An integrated circuit device comprising:
a semiconductor substrate;
a first gate structure and a second gate structure located over the semiconductor substrate and aligned in a line; and
an isolation feature located between and separating the first gate structure and the second gate structure, wherein the isolation feature has a selected shape and includes an air gap having a selected size.

### Claim 18 (depends on 17)

The integrated circuit device of claim 17, wherein the selected shape is a spear-shape, and wherein the selected size is a small air gap.

### Claim 19 (depends on 17)

The integrated circuit device of claim 17, wherein the selected shape is a carrot-shape, and wherein the selected size is a full air gap.

### Claim 20 (depends on 17)

The integrated circuit device of claim 17, wherein the isolation feature has a total depth, and wherein the air gap has a height of at least one half of the total depth.