# US 2025/0159902 A1 · Semiconductor structure and preparation method thereof

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- Number: US 2025/0159902 A1
- Document ID: US20250159902A1
- Status: Published application
- Kind: A1
- Application number: 18/928,224
- Filed: 2024-10-28
- Published: 2025-05-15
- Earliest claimed: 2023-11-09
- Assignees: Xiamen Industrial Technology Research Institute Co., Ltd.
- Applicants: Xiamen Industrial Technology Research Institute Co., Ltd.
- Inventors: Enping CHENG; Taiwei CHIU; Tingying SHEN; Wuxin LI; SZU-CHUN KANG; Anqiao CHEN; Xiaoli SU
- Web page: https://patentgrep.com/patent/US20250159902A1

## CPC

- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10N 70/00: Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching (integrated devices or assemblies of multiple devices H10N79/00)
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor structure and a preparation method thereof are provided. The semiconductor structure includes: a substrate; and a plurality of resistive devices disposed on the substrate; each of the resistive devices includes a lower electrode, a resistive layer and an upper electrode, the resistive layer covers a side wall and at least part of an upper surface of the lower electrode to isolate the lower electrode from the upper electrode, the upper electrode includes a first upper sub-electrode, a second upper sub-electrode and a third upper sub-electrode, the first upper sub-electrode and the second upper sub-electrode are disposed on two sides of the lower electrode respectively, and the third upper sub-electrode is disposed on the lower electrode.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate; and
a plurality of resistive devices, disposed on the substrate; wherein each of the plurality of resistive devices comprises a lower electrode, a resistive layer and an upper electrode; the resistive layer covers a side wall and at least part of an upper surface of the lower electrode to isolate the lower electrode from the upper electrode; the upper electrode comprises a first upper sub-electrode, a second upper sub-electrode and a third upper sub-electrode, the first upper sub-electrode and the second upper sub-electrode are respectively disposed on two sides of the lower electrode, and the third upper sub-electrode is disposed on the lower electrode.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein
upper surfaces of the first upper sub-electrode and the second upper sub-electrode are lower than or flush with the upper surface of the lower electrode.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein
the plurality of resistive devices are arranged in an array in a first direction and a second direction, the first direction and the second direction are parallel to a plane of the substrate, and the first direction intersects with the second direction;
the first upper sub-electrode and the second upper sub-electrode respectively disposed on the two sides of the lower electrode comprises: the first upper sub-electrode and the second upper sub-electrode are respectively disposed on the two sides of the lower electrode in the first direction; and
the semiconductor structure further comprises: a plurality of upper metal layers arranged in the first direction and extending in the second direction, the plurality of upper metal layers are disposed on the upper electrode, and each of the plurality of upper metal layers is electrically connected to each of the first, second, and third upper sub-electrodes.

### Claim 4 (depends on 3)

The semiconductor structure according to claim 3, wherein
the resistive layer covering the side wall and at least part of the upper surface of the lower electrode comprises: the resistive layer covers part of the upper surface of the lower electrode; and
a size of a part of the resistive layer disposed on the upper surface of the lower electrode in the first direction is equal to a size of the third upper sub-electrode in the first direction.

### Claim 5 (depends on 1)

The semiconductor structure according to claim 1, further comprising:
a lower metal layer disposed on the substrate; wherein the lower metal layer is electrically connected to the lower electrode.

### Claim 6

A preparation method for a semiconductor structure, comprising:
providing a substrate; and
forming a plurality of resistive devices on the substrate; wherein each of the plurality of resistive devices comprises a lower electrode, a resistive layer and an upper electrode, the resistive layer covers a side wall and at least part of an upper surface of the lower electrode to isolate the lower electrode from the upper electrode, the upper electrode comprises a first upper sub-electrode, a second upper sub-electrode and a third upper sub-electrode, the first upper sub-electrode and the second upper sub-electrode are respectively disposed on two sides of the lower electrode, and the third upper sub-electrode is disposed on the lower electrode.

### Claim 7 (depends on 6)

The preparation method for the semiconductor structure according to claim 6, wherein a step of forming the plurality of resistive devices on the substrate comprises:
forming the lower electrode on the substrate;
forming the resistive layer completely covering the side wall and the upper surface of the lower electrode;
respectively forming the first upper sub-electrode and the second upper sub-electrode on two sides of the resistive layer;
forming a first dielectric layer, wherein the first dielectric layer covers upper surfaces of the first upper sub-electrode, the second upper sub-electrode and the resistive layer, and fills a gap between adjacent the two first upper sub-electrode and second upper sub-electrode;
etching and removing part of the first dielectric layer disposed on the upper surface of the resistive layer to form a first groove; and
forming the third upper sub-electrode in the first groove.

### Claim 8 (depends on 6)

The preparation method for the semiconductor structure according to claim 6, wherein a step of forming the plurality of resistive devices on the substrate comprises:
forming the lower electrode on the substrate;
forming the resistive layer completely covering the side wall and the upper surface of the lower electrode;
forming a first dielectric layer, wherein the first dielectric layer covers upper surfaces of the first upper sub-electrode, the second upper sub-electrode and the resistive layer, and fills a gap between adjacent the two first upper sub-electrode and second upper sub-electrode;
etching and removing the first dielectric layer disposed on the upper surfaces of the first upper sub-electrode, the second upper sub-electrode and the resistive layer, and the resistive layer disposed on the upper surface of the lower electrode;
forming a first resistive layer covering the first upper sub-electrode, the second upper sub-electrode and the lower electrode;
forming an initial third upper sub-electrode on the first resistive layer;
forming a third upper sub-electrode patterned mask on the initial third upper sub-electrode; and
using the third upper sub-electrode patterned mask to etch and remove the initial third upper sub-electrode and the first resistive layer, wherein the initial third upper sub-electrode and the first resistive layer are not covered with the third upper sub-electrode patterned mask, retaining the initial third upper sub-electrode disposed on the lower electrode to form the third upper sub-electrode, and retaining the first resistive layer disposed below the third upper sub-electrode, the first resistive layer forming one part of the resistive layer.

### Claim 9 (depends on 6)

The preparation method for the semiconductor structure according to claim 6, wherein
upper surfaces of the first upper sub-electrode and the second upper sub-electrode are lower than or flush with the upper surface of the lower electrode.

### Claim 10 (depends on 6)

The preparation method for the semiconductor structure according to claim 6, wherein
the plurality of resistive devices are arranged in an array in a first direction and a second direction, the first direction and the second direction are parallel to a plane of the substrate, and the first direction intersects with the second direction;
a step of disposing the first upper sub-electrode and the second upper sub-electrode on the two sides of the lower electrode respectively comprises: the first upper sub-electrode and the second upper sub-electrode are respectively disposed on the two sides of the lower electrode in the first direction; and
wherein the preparation method for the semiconductor structure further comprises: forming a plurality of upper metal layers arranged in the first direction and extending in the second direction; wherein the plurality of upper metal layers are disposed on the upper electrode, and each of the upper metal layers is electrically connected to each of the first, second, and third upper sub-electrodes.