Error detection and classification at a host device
AssigneeMicron Technology, Inc.
InventorsAaron P. Boehm, Scott E. Schaefer
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Abstract
Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.
Claims20
A host system, comprising:
- receive circuitry configured to receive a codeword, an error detection bit that indicates whether a memory system detected a first type of error in the codeword, and a first set of parity bits;
- syndrome circuitry configured to generate syndrome bits associated with the codeword based at least in part on the first set of parity bits, wherein the syndrome bits indicate whether a second type of error is detected in the codeword;
- and
- a controller configured to generate, based at least in part on the error detection bit and the syndrome bits, an error status for the codeword based at least in part on whether the memory system detected the first type of error in the codeword and whether the second type of error was detected in the codeword.
A host system, comprising:
- receive circuitry configured to receive a set of parity bits associated with a codeword and a first error detection bit that indicates whether a memory system detected a first type of error in the codeword;
- syndrome circuitry configured to generate a set of syndrome bits based at least in part on the set of parity bits;
- error detection bit circuitry configured to generate, based at least in part on the set of syndrome bits, a second error detection bit that indicates whether a second type of error is detected in the codeword;
- and
- a controller configured to generate, based at least in part on the first error detection bit and the second error detection bit, an error status for the codeword based at least in part on whether the memory system detected the first type of error in the codeword and whether the second type of error was detected in the codeword.
A host system, comprising:
- processing circuitry configured to cause the host system to:
- receive a codeword, an error detection bit that indicates whether a memory system detected a first type of error in the codeword, and a first set of parity bits;
- generate syndrome bits associated with the codeword based at least in part on the first set of parity bits, wherein the syndrome bits indicate whether a second type of error is detected in the codeword;
- and
- generate, based at least in part on the error detection bit and the syndrome bits, an error status for the codeword based at least in part on whether the memory system detected the first type of error in the codeword and whether the second type of error was detected in the codeword.
Dependencies are inferred from the claim text.