3d stacked integrated circuits having failure management
AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Life of this patent
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Abstract
A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.
Claims20
A device, comprising:
- a first integrated circuit die;
- and
- the first integrated circuit die connected to a second integrated circuit die by at least one through-silicon via.
A device, comprising:
- a first integrated circuit die;
- and
- a second integrated circuit die stacked on top of the first integrated circuit die, wherein:
- a first functional block of the first integrated circuit die is connected to a first functional block of the second integrated circuit die by a first through-silicon via.
A method comprising:
- receiving, at a volatile memory die of an integrated circuit device, a request from a controller;
- and
- receiving, from the volatile memory die at a processing logic die of the integrated circuit device, the request, wherein the request is transmitted through a first through-silicon via connecting the volatile memory die and the processing logic die.
Dependencies are inferred from the claim text.