# US 2025/0157985 A1 · Semiconductor package with high routing density patch > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0157985 A1 - Document ID: US20250157985A1 - Status: Published application - Kind: A1 - Application number: 19/027,018 - Filed: 2025-01-17 - Published: 2025-05-15 - Earliest claimed: 2015-04-14 - Assignees: Amkor Technology Singapore Holding Pte. Ltd. - Applicants: Amkor Technology Singapore Holding Pte. Ltd. - Inventors: Michael Kelly; Ronald Patrick Huemoeller; David Jon Hiner - Web page: https://patentgrep.com/patent/US20250157985A1 ## CPC - H10W 90/00: Package configurations - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/685: comprising multiple insulating layers - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate} - H10W 70/63: Vias, e.g. via plugs - H10W 72/072: {of bump connectors} - H10W 72/07236: {Soldering or alloying} - H10W 72/073: {of die-attach connectors} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/354: {comprising polymers} - H10W 72/931: {Shapes of bond pads} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less. ## Claims ### Claim 1 A method for semiconductor packaging, the method comprising: bonding a high routing density patch to a first surface of a substrate; and bonding a semiconductor die to the first surface of a substrate and to the high routing density patch; wherein the high routing density patch comprises a denser trace line density than the first substrate. ### Claim 2 (depends on 1) The method according to claim 1, comprising bonding a second semiconductor die to the first surface of the substrate and the high routing density patch, wherein the high routing density patch provides electrical interconnection between the semiconductor die and the second semiconductor die. ### Claim 3 (depends on 1) The method according to claim 1, wherein a thickness of the high routing density patch comprises a BEOL portion and is TSV-less. ### Claim 4 An electronic device, the device comprising: a high routing density patch bonded to a first surface of a substrate; and a semiconductor die bonded to the first surface of a substrate and to the high routing density patch; wherein the high routing density patch comprises a denser trace line density than the first substrate. ### Claim 5 (depends on 4) The device according to claim 4, comprising a second semiconductor die bonded to the first surface of the substrate and to the high routing density patch. ### Claim 6 (depends on 5) The device according to claim 5, wherein the high routing density patch provides electrical interconnection between the semiconductor die and the second semiconductor die. ### Claim 7 (depends on 4) The device according to claim 4, comprising an interposer on which the substrate is positioned. ### Claim 8 (depends on 7) The device according to claim 7, wherein the interposer comprises silicon. ### Claim 9 (depends on 4) The device according to claim 4, wherein the high routing density patch is at least one of: 10 microns or less in thickness; or substantially devoid of semiconductor material. ### Claim 10 (depends on 4) The device according to claim 4, wherein the high routing density patch comprises trace lines at a spacing of approximately 1 μm or less, and the substrate comprises no trace lines at a spacing of less than 1 μm. ### Claim 11 (depends on 4) The device according to claim 4, wherein the substrate is at least one of: 10 microns or less in thickness; or substantially devoid of semiconductor material. ### Claim 12 (depends on 4) The device according to claim 4, wherein an encapsulant material encapsulates at least a portion of the semiconductor die, the high routing density patch, and the first surface of the substrate. ### Claim 13 (depends on 4) The device according to claim 4, wherein a first portion of a thickness of the high routing density patch comprises an inorganic dielectric and metal layer structure. ### Claim 14 (depends on 13) The device according to claim 13, wherein a second portion of the thickness of the high routing density patch comprises an organic dielectric and metal layer structure. ### Claim 15 (depends on 4) The device according to claim 4, wherein a thickness of the high routing density patch comprises a BEOL portion and is TSV-less. ### Claim 16 (depends on 4) The device according to claim 4, wherein the high routing density patch is located between a first surface of the semiconductor die and the first surface of the substrate, and at least a first portion of the first surface of the semiconductor die is uncovered by the high routing density patch. ### Claim 17 An electronic device, the device comprising: a semiconductor die bonded to a first surface of a substrate; and a high routing density patch bonded to a second surface of the substrate opposite to the first surface; wherein the high routing density patch comprises a denser trace line density than the first substrate. ### Claim 18 (depends on 17) The device according to claim 17, comprising a second semiconductor die bonded to the first surface of the substrate. ### Claim 19 (depends on 18) The device according to claim 18, wherein the high routing density patch provides electrical interconnection between the semiconductor die and the second semiconductor die. ### Claim 20 (depends on 17) The device according to claim 17, wherein the high routing density patch has a thickness of 10 microns or less.