# US 2025/0157930 A1 · Integrated circuit semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0157930 A1 - Document ID: US20250157930A1 - Status: Published application - Kind: A1 - Application number: 19/028,311 - Filed: 2025-01-17 - Published: 2025-05-15 - Earliest claimed: 2020-10-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jaechoon Kim; Seunggeol Ryu; Kyungsuk Oh; Keungbeum Kim; Eonsoo Jang - Web page: https://patentgrep.com/patent/US20250157930A1 ## CPC - H10W 20/427: {Power or ground buses} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/42: Vias, e.g. via plugs - H10W 20/481: {on the rear surfaces of the wafers or substrates} - H10W 40/10: Arrangements for heating - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/253: {Semiconductors} - H10W 20/0698: {Local interconnections} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers. ## Claims ### Claim 1 An integrated circuit semiconductor device comprising: a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and including a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising an upper multi-layer interconnect layer connected to the local conductive interconnect via the cell via; and a heat transfer line connected to the upper multi-layer interconnect layer and formed in the cell-level portion and the signal wiring-level portion. ### Claim 2 (depends on 1) The integrated circuit semiconductor device of claim 1, further comprising: a second substrate arranged on the signal wiring-level portion, and a bonding-level portion arranged between the signal wiring-level portion and the second substrate and bonding the signal wiring-level portion to the second substrate. ### Claim 3 (depends on 2) The integrated circuit semiconductor device of claim 2, wherein the bonding-level portion comprises a first bonding pad that is on the signal wiring-level portion and connected to the upper multi-layer interconnect layer and a second bonding pad formed on a lower surface of the second substrate and bonded to the first bonding pad. ### Claim 4 (depends on 2) The integrated circuit semiconductor device of claim 2, wherein the bonding-level portion comprises a set of single bonding pads, each connected to the second substrate and the upper multi-layer interconnect layer of the signal wiring-level portion. ### Claim 5 (depends on 4) The integrated circuit semiconductor device of claim 4, further comprising a heat transfer path in which the heat transfer line, the upper multi-layer interconnect layer, and one of the single bonding pads are all connected in a direction from the signal wiring-level portion toward the second substrate. ### Claim 6 (depends on 2) The integrated circuit semiconductor device of claim 2, wherein the bonding-level portion comprises a first bonding pad that is located on the signal wiring-level portion and connected to the heat transfer line and the upper multi-layer interconnect layer and a second bonding pad that is on a lower surface of the second substrate and bonded to the first bonding pad. ### Claim 7 (depends on 1) The integrated circuit semiconductor device of claim 1, further comprising: a power delivery network-level portion arranged under the second surface of the substrate and comprising a lower multi-layer interconnect layer connected to the rail through via, and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layer. ### Claim 8 (depends on 7) The integrated circuit semiconductor device of claim 7, wherein the buried rail comprises one of a power rail, a ground rail, and a signal rail. ### Claim 9 (depends on 1) The integrated circuit semiconductor device of claim 1, wherein the first surface comprises a front surface of the substrate and the second surface comprises a back surface of the substrate. ### Claim 10 (depends on 1) The integrated circuit semiconductor device of claim 1, wherein the transistor comprises a fin field-effect transistor (finFET), and the local conductive interconnect surrounds a portion of an upper portion of an active fin constituting the finFET. ### Claim 11 (depends on 1) The integrated circuit semiconductor device of claim 1, further comprising a heat transfer through via passing between the first surface and the second surface of the substrate, wherein the heat transfer through via is connected to the heat transfer line. ### Claim 12 An integrated circuit semiconductor device comprising: a first substrate having a first surface and a second surface opposite the first surface; a first through via passing from the first surface to the second surface of the first substrate; a heat transfer through via arranged apart from the first through via and passing from the first surface to the second surface of the first substrate; a cell-level portion arranged on the first surface of the first substrate and comprising a buried conductor connected to the first through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a heat transfer line connected to the heat transfer through via and the upper multi-layer interconnect layers, the heat transfer line formed in the cell-level portion and the signal wiring-level portion; a second substrate arranged on the signal wiring-level portion; and a bonding-level portion arranged between the signal wiring-level portion and the second substrate and bonding the signal wiring-level portion to the second substrate, and comprising a bonding pad connected to an upper via of the upper vias. ### Claim 13 (depends on 12) The integrated circuit semiconductor device of claim 12, further comprising: a power delivery network-level portion arranged under the second surface of the first substrate and comprising a plurality of lower multi-layer interconnect layers connected to the first through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers. ### Claim 14 (depends on 13) The integrated circuit semiconductor device of claim 13, further comprising: a heat transfer path including the lower multi-layer interconnect layers, the lower vias, the heat transfer through via, the heat transfer line, the upper multi-layer interconnect layers, the upper vias, wherein the bonding pad are all connected in a direction from the external connection terminal toward the second substrate. ### Claim 15 (depends on 13) The integrated circuit semiconductor device of claim 13, wherein the buried conductor comprises one of a power rail, a ground rail, and a signal rail, and is arranged on the first substrate to extend in a first direction, and the local conductive interconnect is arranged on the first substrate to extend in a second direction perpendicular to the first direction. ### Claim 16 (depends on 12) The integrated circuit semiconductor device of claim 12, wherein the bonding pad comprises a first bonding pad having a first width and that is arranged on the signal wiring-level portion and connected to the upper via and a second bonding pad having a second width different from the first width and arranged under the second substrate and bonded to the first bonding pad. ### Claim 17 (depends on 12) The integrated circuit semiconductor device of claim 12, wherein the bonding pad comprises a single bonding pad arranged on the signal wiring-level portion and connected to the upper via. ### Claim 18 An integrated circuit semiconductor device comprising: a first substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the first substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a second substrate arranged on the signal wiring-level portion; and a bonding-level portion arranged between the signal wiring-level portion and the second substrate and bonding the signal wiring-level portion to the second substrate, and comprising a bonding pad connected to an upper via of the upper vias. ### Claim 19 (depends on 18) The integrated circuit semiconductor device of claim 18, further comprising: a power delivery network-level portion arranged under the second surface of the first substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other, and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers. ### Claim 20 (depends on 18) The integrated circuit semiconductor device of claim 18, wherein the bonding pad comprises a first bonding pad that is arranged on the signal wiring-level portion, has a first width, and is connected to an upper via of the upper vias, and a second bonding pad that is arranged under the second substrate and is bonded to the first bonding pad.