# US 2025/0157902 A1 · Semiconductor package including a conductive pillar > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0157902 A1 - Document ID: US20250157902A1 - Status: Published application - Kind: A1 - Application number: 18/938,811 - Filed: 2024-11-06 - Published: 2025-05-15 - Earliest claimed: 2023-11-10 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Junghoon KANG; Kiju LEE - Web page: https://patentgrep.com/patent/US20250157902A1 ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/66: Conductive materials thereof - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes: a first redistribution structure; a second redistribution structure arranged on the first redistribution structure; a first conductive pillar arranged spaced apart from the second redistribution structure and arranged on the first redistribution structure; a first chip arranged on the second redistribution structure; a first molding member covering the first chip and disposed on the second redistribution structure; a third redistribution structure arranged on the first molding member; a second chip arranged on the third redistribution structure; a second molding member covering the first conductive pillar and the first molding member; and a fourth redistribution structure arranged on the second molding member, wherein a first film is arranged on a first surface of the first conductive pillar, and the first film includes tin (Sn). ## Claims ### Claim 1 A semiconductor package comprising: a first redistribution structure; a second redistribution structure arranged on the first redistribution structure; a first conductive pillar spaced apart from the second redistribution structure and arranged on the first redistribution structure; a first chip arranged on the second redistribution structure; a first molding member covering the first chip and disposed on the second redistribution structure; a third redistribution structure arranged on the first molding member; a second chip arranged on the third redistribution structure; a second molding member covering the first conductive pillar and the first molding member; and a fourth redistribution structure arranged on the second molding member, wherein a first film is arranged on a first surface of the first conductive pillar, and the first film includes tin (Sn). ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first film covers a second surface of the first conductive pillar. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein a thickness of the first film is in a range from about 1 μm to about 3 μm. ### Claim 4 (depends on 2) The semiconductor package of claim 2, wherein a third surface of the first conductive pillar is covered by the fourth redistribution structure. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein an aspect ratio of the first conductive pillar is in a range from 1:2 to 1:5. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein a size of the first chip is less than a size of the second chip. ### Claim 7 (depends on 6) The semiconductor package of claim 6, further comprising a second conductive pillar arranged spaced apart from the first chip and disposed on the second redistribution structure. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein a third chip is arranged on the fourth redistribution structure. ### Claim 9 (depends on 1) The semiconductor package of claim 1, further comprising a second through via penetrating from an upper surface of the first molding member to an upper surface of the first chip in a vertical direction. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein a size of the first redistribution structure is greater than a size of the second redistribution structure. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein a melting point of the first film is lower than a melting point of the first conductive pillar. ### Claim 12 A semiconductor package comprising: a first redistribution structure including an upper surface, a lower surface opposite to the upper surface, and a first upper pad disposed at the upper surface; a second redistribution structure arranged on the first redistribution structure; a first conductive pillar spaced apart from the second redistribution structure and on the first upper pad of the first redistribution structure; a plurality of solder balls arranged between the first upper pad and the first conductive pillar; a first chip arranged on the second redistribution structure; a first molding member covering the first chip and disposed on the second redistribution structure; a third redistribution structure arranged on the first molding member; a second chip arranged on the third redistribution structure; a second molding member covering the first conductive pillar and the first molding member; and a fourth redistribution structure arranged on the second molding member. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein a junction layer covering the plurality of solder balls is arranged between the first upper pad and the first conductive pillar. ### Claim 14 (depends on 12) The semiconductor package of claim 12, wherein an aspect ratio of the first conductive pillar is in a range from 1:2 to 1:5. ### Claim 15 (depends on 12) The semiconductor package of claim 12, wherein a length of the first chip in a first horizontal direction is smaller than a length of the second chip in a first horizontal direction. ### Claim 16 (depends on 15) The semiconductor package of claim 15, further comprising a second conductive pillar arranged spaced apart from the first chip on an upper surface of the second redistribution structure. ### Claim 17 (depends on 12) The semiconductor package of claim 12, wherein a third chip is arranged on the fourth redistribution structure. ### Claim 18 A semiconductor package comprising: a first redistribution structure including an upper surface, a lower surface opposite to the upper surface, and a first upper pad disposed in the first redistribution structure; a second redistribution structure arranged on the first redistribution structure; a first bump arranged between the first redistribution structure and the second redistribution structure; a first conductive pillar spaced apart from the second redistribution structure and on the first upper pad of the first redistribution structure; a first film covering a lower surface and a lateral surface of the first conductive pillar; a first chip arranged on the second redistribution structure; a second conductive pillar arranged spaced apart from the first chip and disposed on the second redistribution structure; a first molding member covering the first chip and the second conductive pillar and disposed on the second redistribution structure; a third redistribution structure arranged on the first molding member; a second chip arranged on the third redistribution structure and having a size greater than a size of the first chip; a second molding member covering the first conductive pillar and the first molding member; and a fourth redistribution structure arranged on the second molding member, wherein a thickness of the first film is in a range from about 1 μm to about 3 μm, a melting point of the first film is lower than a melting point of the first conductive pillar, and an aspect ratio of the first conductive pillar is in a range from 1:2 to 1:5. ### Claim 19 (depends on 18) The semiconductor package of claim 18, wherein the first film comprises tin. ### Claim 20 (depends on 18) The semiconductor package of claim 18, wherein a third chip is arranged on the fourth redistribution structure.