# US 2025/0157744 A1 · Multilayer ceramic electronic component and mounting structure of multilayer ceramic electronic component > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0157744 A1 - Document ID: US20250157744A1 - Status: Published application - Kind: A1 - Application number: 19/021,403 - Filed: 2025-01-15 - Published: 2025-05-15 - Earliest claimed: 2022-08-02 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Kentaro FUJIWARA; Tatsunori YASUDA - Web page: https://patentgrep.com/patent/US20250157744A1 ## CPC - H01G 4/30: Stacked capacitors (H01G4/33 takes precedence) - H01G 4/12: Ceramic dielectrics {(H01G4/085 takes precedence)} - H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor - H01G 4/2325: {characterised by the material of the terminals} - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) ## Abstract In a multilayer ceramic electronic component, a first outer electrode includes a first base electrode layer, a first lower plating layer on the first base electrode layer, and a first upper plating layer on the first lower plating layer except for a first plating exposed region exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region, and a second outer electrode includes a second base electrode layer, a second lower plating layer on the second base electrode layer, and a second upper plating layer on the second lower plating layer except for a second plating exposed region exposed on a surface of the second outer electrode so that the second lower plating layer includes the second plating exposed region. ## Claims ### Claim 1 A multilayer ceramic electronic component comprising: a multilayer body including a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in a height direction, a first end surface and a second end surface facing each other in a length direction orthogonal or substantially orthogonal to the height direction, and a first side surface and a second side surface facing each other in a width direction orthogonal or substantially orthogonal to the height direction and the length direction; a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface; a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the second end surface; a first outer electrode on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers; and a second outer electrode on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the second inner electrode layers; wherein the first outer electrode includes a first base electrode layer on the multilayer body, a first lower plating layer on the first base electrode layer, and a first upper plating layer on the first lower plating layer except for a first plating exposed region exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region; and the second outer electrode includes a second base electrode layer on the multilayer body, a second lower plating layer on the second base electrode layer, and a second upper plating layer on the second lower plating layer except for a second plating exposed region exposed on a surface of the second outer electrode so that the second lower plating layer includes the second plating exposed region. ### Claim 2 A multilayer ceramic electronic component comprising: a multilayer body including a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in a height direction, a first end surface and a second end surface facing each other in a length direction orthogonal or substantially orthogonal to the height direction, and a first side surface and a second side surface facing each other in a width direction orthogonal or substantially orthogonal to the height direction and the length direction; a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface and the second end surface; a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the first side surface and the second side surface; a first outer electrode on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers; a second outer electrode on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers; a third outer electrode on the first side surface, extending from the first side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers; and a fourth outer electrode on the second side surface, extending from the second side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers; wherein the first outer electrode includes a first base electrode layer on the multilayer body, a first lower plating layer on the first base electrode layer, and a first upper plating layer on the first lower plating layer except for a first plating exposed region exposed on a surface of the first outer electrode so that the first lower plating layer includes the first plating exposed region; the second outer electrode includes a second base electrode layer on the multilayer body, a second lower plating layer on the second base electrode layer, and a second upper plating layer on the second lower plating layer except for a second plating exposed region exposed on a surface of the second outer electrode so that the second lower plating layer has the second plating exposed region; the third outer electrode includes a third base electrode layer on the multilayer body, a third lower plating layer on the third base electrode layer, and a third upper plating layer on the third lower plating layer; and the fourth outer electrode includes a fourth base electrode layer on the multilayer body, a fourth lower plating layer on the fourth base electrode layer, and a fourth upper plating layer on the fourth lower plating layer. ### Claim 3 (depends on 2) The multilayer ceramic electronic component according to claim 2, wherein the third upper plating layer is provided on the third lower plating layer except for a third plating exposed region exposed on a surface of the third outer electrode so that the third lower plating layer includes the third plating exposed region; and the fourth upper plating layer is provided on the fourth lower plating layer except for a fourth plating exposed region exposed on a surface of the fourth outer electrode so that the fourth lower plating layer has the fourth plating exposed region. ### Claim 4 A multilayer ceramic electronic component comprising: a multilayer body including a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in a height direction, a first end surface and a second end surface facing each other in a length direction orthogonal or substantially orthogonal to the height direction, and a first side surface and a second side surface facing each other in a width direction orthogonal or substantially orthogonal to the height direction and the length direction; a plurality of first inner electrode layers on the plurality of ceramic layers and extending to the first end surface and the second end surface; a plurality of second inner electrode layers on the plurality of ceramic layers and extending to the first side surface and the second side surface; a first outer electrode on the first end surface, extending from the first end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers; a second outer electrode on the second end surface, extending from the second end surface to a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and being connected to the first inner electrode layers; a third outer electrode on the first side surface, extending from the first side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers; and a fourth outer electrode on the second side surface, extending from the second side surface to a portion of the first main surface and a portion of the second main surface, and being connected to the second inner electrode layers; wherein the first outer electrode includes a first base electrode layer on the multilayer body, a first lower plating layer on the first base electrode layer, and a first upper plating layer on the first lower plating layer; the second outer electrode includes a second base electrode layer on the multilayer body, a second lower plating layer on the second base electrode layer, and a second upper plating layer on the second lower plating layer; the third outer electrode includes a third base electrode layer on the multilayer body, a third lower plating layer on the third base electrode layer, and a third upper plating layer on the third lower plating layer except for a third plating exposed region exposed on a surface of the third outer electrode so that the third lower plating layer includes the third plating exposed region; and the fourth outer electrode includes a fourth base electrode layer on the multilayer body, a fourth lower plating layer on the fourth base electrode layer, and a fourth upper plating layer on the fourth lower plating layer except for a fourth plating exposed region exposed on a surface of the fourth outer electrode so that the fourth lower plating layer includes the fourth plating exposed region. ### Claim 5 (depends on 1) The multilayer ceramic electronic component according to claim 1, wherein a first ratio of an area of the first plating exposed region to an area of an exposed region of the first outer electrode on the first main surface when viewed in a direction of the first main surface is about 0.4% or more and about 83.4% or less; and a second ratio of an area of the second plating exposed region to an area of an exposed region of the second outer electrode on the first main surface when viewed in the direction of the first main surface is about 0.4% or more and about 83.4% or less. ### Claim 6 (depends on 5) The multilayer ceramic electronic component according to claim 5, wherein the first ratio and the second ratio are about 1.17% or more and about 83.4% or less. ### Claim 7 (depends on 6) The multilayer ceramic electronic component according to claim 6, wherein the first ratio and the second ratio are about 1.40% or more and about 83.4% or less. ### Claim 8 (depends on 7) The multilayer ceramic electronic component according to claim 7, wherein the first ratio and the second ratio are about 1.40% or more and about 25.0% or less. ### Claim 9 (depends on 1) The multilayer ceramic electronic component according to claim 1, wherein the first plating exposed region is on the first main surface. ### Claim 10 (depends on 1) The multilayer ceramic electronic component according to claim 1, wherein a thickness of the first lower plating layer is about 2 μm or more and about 7 μm or less. ### Claim 11 (depends on 2) The multilayer ceramic electronic component according to claim 2, wherein a first ratio of an area of the first plating exposed region to an area of an exposed region of the first outer electrode on the first main surface when viewed in a direction of the first main surface is about 0.4% or more and about 83.4% or less; and a second ratio of an area of the second plating exposed region to an area of an exposed region of the second outer electrode on the first main surface when viewed in the direction of the first main surface is about 0.4% or more and about 83.4% or less. ### Claim 12 (depends on 11) The multilayer ceramic electronic component according to claim 11, wherein the first ratio and the second ratio are about 1.17% or more and about 83.4% or less. ### Claim 13 (depends on 12) The multilayer ceramic electronic component according to claim 12, wherein the first ratio and the second ratio are about 1.40% or more and about 83.4% or less. ### Claim 14 (depends on 13) The multilayer ceramic electronic component according to claim 13, wherein the first ratio and the second ratio are about 1.40% or more and about 25.0% or less. ### Claim 15 (depends on 2) The multilayer ceramic electronic component according to claim 2, wherein the first plating exposed region is on the first main surface. ### Claim 16 (depends on 1) The multilayer ceramic electronic component according to claim 1, wherein a portion of the first base electrode layer is exposed on the first main surface. ### Claim 17 (depends on 3) The multilayer ceramic electronic component according to claim 3, wherein at least one of a third ratio of an area of the third plating exposed region to an area of an exposed region of the third outer electrode on the first main surface when viewed in a direction of the first main surface and a fourth ratio of an area of the fourth plating exposed region to an area of an exposed region of the fourth outer electrode on the first main surface when viewed in the direction of the first main surface is about 0.4% or more and about 83.4% or less. ### Claim 18 (depends on 1) A mounting structure of a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to claim 1; and a mounting substrate on which the multilayer ceramic electronic component is mounted; wherein the first plating exposed region is provided on the first main surface, and the multilayer ceramic electronic component is mounted such that the second main surface faces the mounting substrate. ### Claim 19 (depends on 2) A mounting structure of a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to claim 2; and a mounting substrate on which the multilayer ceramic electronic component is mounted; wherein a positive potential is applied to the first outer electrode and the second outer electrode. ### Claim 20 (depends on 4) A mounting structure of a multilayer ceramic electronic component, comprising: the multilayer ceramic electronic component according to claim 4; and a mounting substrate on which the multilayer ceramic electronic component is mounted; wherein a positive potential is applied to the third outer electrode and the fourth outer electrode.