# US 2025/0157553 A1 · Memory device and method for controlling verification voltage of memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0157553 A1 - Document ID: US20250157553A1 - Status: Published application - Kind: A1 - Application number: 18/882,728 - Filed: 2024-09-11 - Published: 2025-05-15 - Earliest claimed: 2023-11-14 - Assignees: eMemory Technology Inc. - Applicants: eMemory Technology Inc. - Inventors: Wei-Ming Ku; Wei-Chiang Ong; Chih-Yang Huang; Che-Wei Chang - Web page: https://patentgrep.com/patent/US20250157553A1 ## CPC - H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - H03K 19/018521: {of complementary type, e.g. CMOS} - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling} - H10D 30/685: {from the channel} - H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate} - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector. ## Claims ### Claim 1 A method for controlling a verification voltage of a memory device, comprising: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a first memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the first memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector. ### Claim 2 (depends on 1) The method of claim 1, wherein in each verification cycle of the first memory sector, the charge pump circuit pulls the verification voltage to the predetermined level for a fixed number of times. ### Claim 3 (depends on 1) The method of claim 1, wherein multiple memory sectors of the memory device comprise different numbers of memory cells, and the multiple memory sectors respectively correspond to multiple values of the bit count of data bits verified in one verification cycle. ### Claim 4 (depends on 3) The method of claim 3, wherein a number of memory cells within the first memory sector among the multiple memory sectors is greater than a number of memory cells within a second memory sector among the multiple memory sectors, and a value of the bit count of data bits of the first memory sector verified in one verification cycle is greater than a value of the bit count of data bits of the second memory sector verified in one verification cycle. ### Claim 5 (depends on 4) The method of claim 4, wherein a number of enabled sense amplifiers of the memory device for verifying the first memory sector in one verification cycle is greater than a number of enabled sense amplifiers of the memory device for verifying the second memory sector in one verification cycle. ### Claim 6 (depends on 1) The method of claim 1, wherein K sense amplifiers of the memory device are enabled in the present verification cycle to verify the K data bits, and the other sense amplifiers of the memory device are disabled in the present verification cycle. ### Claim 7 (depends on 1) The method of claim 1, wherein the electrical characteristics of the first memory sector comprise a number of memory cells of the first memory sector. ### Claim 8 (depends on 1) The method of claim 1, wherein the electrical characteristics of the first memory sector comprise: a cell current of a memory cell of the first memory sector; a sensing time for verifying the K data bits; a maximum acceptable voltage drop of the verification voltage in the sensing time; and parasitic capacitance of a source line of the first memory sector. ### Claim 9 (depends on 8) The method of claim 8, wherein in each verification cycle of the first memory sector, a practical voltage drop of the verification voltage is not greater than the maximum acceptable voltage drop. ### Claim 10 (depends on 1) The method of claim 1, wherein verification of the whole first memory sector of the memory device is completed in multiple verification cycles, and during each of the multiple verification cycles, the verification voltage is pulled to the predetermined level only once. ### Claim 11 (depends on 1) The method of claim 1, wherein when the charge pump stops pulling up the verification voltage, the verification voltage keeps decreasing until an end time point of the present verification cycle. ### Claim 12 A memory device, comprising: a first memory sector; a controller, configured to determine a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of the first memory sector, wherein K is a positive integer; and a charge pump circuit, coupled to the controller, and configured to transmit a verification voltage to the first memory sector; wherein: the controller is configured to control the charge pump circuit to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle; the controller is further configured to control the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and K data bits written into the memory device are verified based on the verification voltage after the verification time point of the present verification cycle. ### Claim 13 (depends on 12) The memory device of claim 12, wherein in each verification cycle of the first memory sector, the charge pump circuit pulls the verification voltage to the predetermined level for a fixed number of times. ### Claim 14 (depends on 12) The memory device of claim 12, wherein multiple memory sectors of the memory device comprise different numbers of memory cells, and the multiple memory sectors respectively correspond to multiple values of the bit count of data bits verified in one verification cycle. ### Claim 15 (depends on 14) The memory device of claim 14, wherein a number of memory cells within the first memory sector among the multiple memory sectors is greater than a number of memory cells within a second memory sector among the multiple memory sectors, and a value of the bit count of data bits of the first memory sector verified in one verification cycle is greater than a value of the bit count of data bits of the second memory sector verified in one verification cycle. ### Claim 16 (depends on 15) The memory device of claim 15, wherein a number of enabled sense amplifiers of the memory device for verifying the first memory sector in one verification cycle is greater than a number of enabled sense amplifiers of the memory device for verifying the second memory sector in one verification cycle. ### Claim 17 (depends on 12) The memory device of claim 12, wherein K sense amplifiers of the memory device are enabled in the present verification cycle to verify the K data bits, and the other sense amplifiers of the memory device are disabled in the present verification cycle. ### Claim 18 (depends on 12) The memory device of claim 12, wherein the electrical characteristics of the first memory sector comprise a number of memory cells of the first memory sector. ### Claim 19 (depends on 12) The memory device of claim 12, wherein the electrical characteristics of the first memory sector comprise: a cell current of a memory cell of the first memory sector; a sensing time for verifying the K data bits; a maximum acceptable voltage drop of the verification voltage in the sensing time; and parasitic capacitance of a source line of the first memory sector. ### Claim 20 (depends on 12) The memory device of claim 12, wherein in each verification cycle of the first memory sector, a practical voltage drop of the verification voltage is not greater than the maximum acceptable voltage drop. ### Claim 21 (depends on 12) The memory device of claim 12, wherein verification of the whole first memory sector of the memory device is completed in multiple verification cycles; and during each of the multiple verification cycles, the verification voltage is pulled to the predetermined level only once. ### Claim 22 (depends on 12) The memory device of claim 12, wherein when the charge pump stops pulling up the verification voltage, the verification voltage keeps decreasing until an end time point of the present verification cycle.