Semiconductor memory devices having efficient serializers therein for transferring data
AssigneeSamsung Electronics Co., Ltd.
InventorsSanguk Lee, Daehyun Kwon, Jang-Woo Ryu, Hangi Jung
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Abstract
An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.
Claims20
A serializer of a semiconductor memory device, the serializer comprising:
- a plurality of multiplexers, each multiplexer configured to output an inverted data signal based on one of parallel data and two clock signals having mutually different phases;
- and
- a serializing circuit configured to output serial data by logically combining inverted data signals output from the plurality of multiplexers,
- wherein each of the plurality of multiplexers acquires inverted data of one of the parallel data between rising edges of the two clock signals and generates the inverted data signals.
An integrated circuit memory device, comprising:
- a memory core;
- control logic configured to control the memory core to:
- (i) output parallel data, and (ii) generate multiple internal clock signals in response to a clock signal received from a host;
- and
- a data transmitting unit including a serializer configured to convert the parallel data into serial data, said serializer comprising:
- a plurality of multiplexers that are each configured to output a respective inverted data signal based on one of the parallel data and two of the internal clock signals having different phases relative to each other;
- and
- a serializing circuit configured to output the serial data by logically combining the inverted data signals output from the plurality of multiplexers;
- and
- wherein each of the plurality of multiplexers generates a corresponding one of the inverted data signals by inverting the one of the parallel data between rising edges of the corresponding two internal clock signals.
A memory system, comprising:
- an integrated circuit memory device;
- and
- a memory controller configured to transmit a clock signal to the integrated circuit memory device,
- wherein the integrated circuit memory device includes:
- a memory core;
- control logic configured to control the memory core to:
- (i) output parallel data, and (ii) generate multiple internal clock signals in response to the clock signal received from the memory controller;
- and
- a data transmitting unit including a serializer configured to convert the parallel data into serial data and transmit the serial data to the memory controller, said serializer comprising:
- a plurality of multiplexers that are each configured to output a respective inverted data signal based on one of the parallel data and two of the internal clock signals having different phases relative to each other;
- and
- a serializing circuit configured to output the serial data by logically combining the inverted data signals output from the plurality of multiplexers,
- wherein each of the plurality of multiplexers acquires inverted data of the one of the parallel data between rising edges of the corresponding two internal clock signals and generates therefrom a corresponding one of the inverted data signals.
Dependencies are inferred from the claim text.