# US 2025/0157504 A1 · Memory device, memory system, and operation method of memory device

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- Number: US 2025/0157504 A1
- Document ID: US20250157504A1
- Status: Published application
- Kind: A1
- Application number: 18/977,329
- Filed: 2024-12-11
- Published: 2025-05-15
- Earliest claimed: 2018-05-25
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: DONGHUN LEE; DAESIK MOON; YOUNG-SOO SOHN; YOUNG-HOON SON; KI-SEOK OH; CHANGKYO LEE; HYUN-YOON CHO; KYUNG-SOO HA; SEOKHUN HYUN
- Web page: https://patentgrep.com/patent/US20250157504A1

## CPC

- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1087: {Data input latches}
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50008: {of impedance}
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

## Claims

### Claim 1

An operation method of a memory device, the method comprising:
selecting, as a ZQ mode, one of a background calibration mode and a command-based calibration mode based on first information stored in a first mode register;
performing a ZQ calibration based on the selected ZQ mode,
wherein the performing a ZQ calibration based on the selected ZQ mode comprises:
when the selected ZQ mode indicates the command-based calibration mode, performing the ZQ calibration in response to a ZQCal start command received from an external memory controller; and
when the selected ZQ mode indicates the background calibration mode, performing the ZQ calibration with a time interval corresponding second information specified in the first mode register, and
wherein when the selected ZQ mode indicates the background calibration mode, the ZQCal start command from the external memory controller is ignored.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first mode register corresponds to a MR28 of the memory device,
wherein the first information is stored in an OP[5] of the MR28, and
wherein the second information is stored in OP[3:2] of the MR28.

### Claim 3 (depends on 1)

The method of claim 1, wherein the performing a ZQ calibration based on the selected ZQ mode further comprises:
when the selected ZQ mode indicates the background calibration mode:
receiving a ZQCal latch command from the external memory controller; and
loading a new ZQ code onto a driver which drives a data line in response to the ZQCal latch command.

### Claim 4 (depends on 3)

The method of claim 3, wherein the performing a ZQ calibration based on the selected ZQ mode further comprises:
when the selected ZQ mode indicates the background calibration mode:
setting a ZQ update flag (ZQUF) in a second mode register;
receiving a mode register read command from the external memory controller; and
transmitting the ZQ update flag to the external memory controller in response to the mode register read.

### Claim 5 (depends on 4)

The method of claim 4, wherein when the selected ZQ mode indicates the background calibration mode, the mode register read command is periodically received from the external memory controller.

### Claim 6 (depends on 4)

The method of claim 4, wherein the second mode register includes a MR4 of the memory device, and
wherein information about the ZQUF is stored in OP[5] of the MR4.

### Claim 7 (depends on 4)

The method of claim 4, further comprising:
when the selected ZQ mode indicates the background calibration mode:
resetting the ZQUF in the second mode register in response to loading the new ZQ code onto the driver.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
periodically receiving the ZQCal start command from the external memory device.

### Claim 9 (depends on 1)

The method of claim 1, wherein the performing a ZQ calibration based on the selected ZQ mode further comprises:
when the selected ZQ mode indicates the command-based calibration mode:
receiving a ZQCal latch command from the external memory controller after a predefined time passed from a time receiving the ZQ start command; and
loading a new ZQ code onto a driver which drives a data line in response to the ZQCal latch command.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
detecting activation of a dynamic voltage and frequency scaling (DVFSQ) based on a third mode register;
setting a ZQ stop information in the first mode register in response to the activation of the DVFSQ; and
stopping the ZQ calibration based on the background calibration mode while the ZQ stop information is set in the first mode in response,
wherein the first mode register corresponds to a MR28 of the memory device, and
wherein the ZQ stop information is stored in an OP[1] of the MR28.

### Claim 11

An operation method of a memory controller configured to control a memory device, the method comprising:
transmitting a mode register write (MRW) command to the memory device for setting, as a ZQ mode, one of a background calibration mode and a command-based calibration mode in a first mode register of the memory device; and
controlling the memory device to perform a ZQ calibration based on the ZQ mode which is set in the first mode register of the memory device,
wherein when the command-based calibration mode is set in the first mode register as the ZQ mode, the memory device performs the ZQ calibration in response to a ZQCal start command received from the memory controller; and
wherein when the background calibration mode is set in the first mode register, the memory device the ZQ calibration with a time interval corresponding second information specified in the first mode register, and
wherein when the background calibration mode is set in the first mode register, the memory device ignores the ZQCal start command from the memory controller.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
when the background calibration mode is set in the first mode register, periodically transmitting a mode register read (MRR) command to the memory device.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
when the background calibration mode is set in the first mode register, transmitting a ZQCal latch command to the memory device in response to the ZQUF being 1.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
periodically transmitting the ZQCal start command to the memory device when the command-based calibration mode is set in the first mode register as the ZQ mode.

### Claim 15 (depends on 14)

The method of claim 14, wherein the ZQCal start command is transmitted to the memory device when a dynamic voltage and frequency scaling (DVFSQ) is not active.

### Claim 16

A memory system, comprising:
a memory device including a first mode register; and
a memory controller configured to control the memory device to perform a ZQ calibration, wherein the memory device is configured to:
select, as the ZQ mode, one of a background calibration mode and a command-based calibration mode based in the first mode register,
when the selected ZQ mode indicates the command-based calibration mode, perform the ZQ calibration in response to a ZQCal start command received from the memory controller; and
when the selected ZQ mode indicates the background calibration mode, perform the ZQ calibration with a time interval corresponding second information specified in the first mode register, and
wherein when the selected ZQ mode indicates the background calibration mode, the memory controller is further configured to ignore the ZQCal start command from the memory controller.

### Claim 17 (depends on 16)

The memory system of claim 16, wherein the memory controller is further configured to transmit a mode register write (MRW) command to the memory device for setting, as the ZQ mode, one of the background calibration mode and the command-based calibration mode in the first mode register of the memory device.

### Claim 18 (depends on 16)

The memory system of claim 16, wherein when the selected ZQ mode indicates the background calibration mode, the memory controller is further configured to periodically transmit a mode register read (MRR) command to the memory device.

### Claim 19 (depends on 18)

The memory system of claim 18, wherein the memory device is further configured to provide a ZQ update flag (ZQUF) to the memory controller in response to the MRR command.

### Claim 20 (depends on 19)

The memory system of claim 19, wherein the memory controller is further configured to transmit a ZQCal latch command to the memory device in response to the ZQUE being 1.