Hardware acceleration circuit, data processing acceleration method, chip, and accelerator

A hardware acceleration circuit, comprising:

• an exponential function module, configured to obtain a plurality of exponential function values of a plurality of data elements in a data set;
• an adder, configured to obtain an addition operation result of the plurality of exponential function values;
• a first processing circuit, configured to perform preset processing on the addition operation result, to process the addition operation result into at least first data and second data, wherein a length of the addition operation result is N1 bits, a length of the first data is N2 bits, a length of the second data is N3 bits, and both N2 and N3 are less than N1;
• a second processing circuit, configured to perform preset processing on at least the first data and the second data, to obtain a reciprocal of the addition operation result;
• and
• a third processing circuit, configured to perform preset processing on an exponential function value of an ith data element in the plurality of data elements and the reciprocal, to obtain a specific function value of the ith data element.