Logic cell with small cell delay

A semiconductor structure, comprising:

• a semiconductor substrate;
• and
• a logic cell with a logic function, and comprising:
• a plurality of P-type transistors in a first active region over the semiconductor substrate, each comprising a first gate electrode extending along a first direction;
• a plurality of N-type transistors in a second active region over the semiconductor substrate, wherein each of the N-type transistors shares the first gate electrode with a respective P-type transistor;
• a first isolation structure and a second isolation structure on opposite edges of the first active region and opposite edges of the second active region, and extending along the first direction;
• a first transistor in the first active region and between the first isolation structure and the P-type transistors, comprising a second gate electrode extending along the first direction;
• a second transistor in the first active region and between the second isolation structure and the P-type transistors, comprising a third gate electrode extending along the first direction;
• a third transistor in the second active region and between the first isolation structure and the N-type transistors, wherein the first and third transistors share the second gate electrode;
• and
• a fourth transistor in the second active region and between the second isolation structure and the N-type transistors, wherein the second and fourth transistors share the third gate electrode,
• wherein the P-type transistors and the N-type transistors are configured to perform the logic function.