Integrated chip with a gate structure disposed within a trench
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYong-Sheng Huang, Ming Chyi Liu
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Abstract
The present disclosure relates to an integrated chip comprising a substrate comprising a pair of sidewalls defining a first trench. A first gate structure is in the first trench and comprises a first conductive structure, a first dielectric structure between the first conductive structure and the substrate, a second conductive structure, and a second dielectric structure between the second conductive structure and the substrate. The first conductive structure and the second conductive structure are spaced laterally apart from one another between the pair of sidewalls.
Claims20
An integrated chip, comprising:
- a substrate comprising a pair of sidewalls defining a first trench;
- and
- a first gate structure in the first trench and comprising a first conductive structure, a first dielectric structure between the first conductive structure and the substrate, a second conductive structure, and a second dielectric structure between the second conductive structure and the substrate, wherein the first conductive structure and the second conductive structure are spaced laterally apart from one another between the pair of sidewalls.
An integrated chip, comprising:
- a pair of source/drain regions laterally spaced from one another in a substrate;
- a first gate electrode embedded in the substrate;
- a second gate electrode embedded in the substrate and adjacent to the first gate electrode, wherein the first gate electrode and the second gate electrode are spaced between the pair of source/drain regions;
- and
- a first dielectric structure in the substrate and laterally separating an outer sidewall of the first gate electrode from an outer sidewall of the second gate electrode.
An integrated chip, comprising:
- a select gate embedded in a substrate;
- a memory gate embedded in the substrate and adjacent to the select gate;
- and
- a first source/drain region abutting the select gate;
- and
- a second source/drain region abutting the memory gate.
Dependencies are inferred from the claim text.