US 2025/0150089 A1Published application

Oversampled analog to digital converter

OwnerAmit Kumar Guptainventor

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Abstract

An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (n-m)-bit RDAC to provide an intermediate voltage responsive to the n-m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.

Claims20

Dependent claims

An analog-to-digital converter (ADC), comprising:

an input adapted to receive an input voltage;
an output;
a comparator having a first input coupled to the input of the ADC, a second input, and an output, the comparator configured to provide a comparator output at the output responsive to the input voltage and a digital-to-analog converter (DAC) output voltage;
a successive-approximation register (SAR) circuit including an input coupled to the output of the comparator and including a SAR that is configured to store an n-bit digital code that is initialized to an initial value at a beginning of a conversion phase of the ADC, wherein the SAR circuit is configured to:
provide the n-bit digital code as an output at an output of the SAR circuit;
and
update the n-bit digital code responsive to the comparator output, wherein the output of the ADC is responsive to the n-bit digital code at an end of the conversion phase;
and
a DAC having an input and having an output coupled to the second input of the comparator, the DAC configured to provide the DAC output voltage responsive to the n-bit digital code and a reference voltage, wherein the DAC includes:
an m-bit capacitive DAC (CDAC);
and
an (n-m)-bit resistive DAC (RDAC) coupled between the input of the DAC and the m-bit CDAC, the RDAC configured to provide an intermediate DAC voltage responsive to the n-m least-significant bits of the n-bit digital code and the reference voltage,
wherein the m-bit CDAC is configured to provide the DAC output voltage responsive to the m most-significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage.

10 more elements

An analog-to-digital converter (ADC) having an input operable to receive an input voltage and an output operable to provide a digital representation of the input voltage, the ADC comprising:

a comparator having a first input coupled to the input of the ADC, a second input, and an output, the comparator configured to provide a comparator output at the output responsive to the input voltage and a digital-to-analog converter (DAC) output voltage;
a DAC having an input and having an output coupled to the second input of the comparator, the DAC configured to provide the DAC output voltage responsive to an n-bit digital code from a successive-approximation register (SAR) circuit and a reference voltage, wherein the DAC includes:
an m-bit capacitive DAC (CDAC), wherein m is an integer greater than zero but less than n;
and
an (n-m)-bit resistive DAC (RDAC) coupled between the input of the DAC and the m-bit CDAC, the RDAC configured to provide an intermediate DAC voltage responsive to the n-m least-significant bits of the n-bit digital code and the reference voltage,
wherein the m-bit CDAC is configured to provide the DAC output voltage responsive to the m most-significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage;
and
wherein an output of the ADC is based on a sum of the n-bit digital codes at an end of each of 2m conversion sub-phases.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/014,325Filed 9 Jan 2025
Priority: 4 Apr 2022
Published: 8 May 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03M 1/462
With digital/analogue converter for supplying reference values to converter: details of the control circuitry, e.g. of the successive…
H03M 1/0658
In the time domain, e.g. using intended jitter as a dither signal: by calculating a running average of a number of subsequent samples
H03M 1/066
In the time domain, e.g. using intended jitter as a dither signal: by continuously permuting the elements used, i.e. dynamic element matching
H03M 1/0697
Using redundancy: in time, e.g. using additional comparison cycles

Family

Application63/327,079Us provisional application · filed 4 Apr 2022
Application17/874,750Continuation · filed 27 Jul 2022
Application19/014,325Continuation
US 12,231,142 B2Related patent
US 2023/0318615 A1Published application
US 2025/0150089 A1This patent

From the US filing history. Foreign family members aren’t listed.