Low-noise speedy duty cycle detector and method thereof

A duty cycle detector comprising:

• a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state during an even cycle, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state during the even cycle;
• a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state;
• a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state;
• a first discharging network configured to discharge the first capacitor when the clock is in the first state during an odd cycle;
• and
• a second discharging network configured to discharge the second capacitor when the clock is in a second state during the odd cycle.

A method of duty cycle detection comprising:

• receiving a clock that cyclically alternates between an even cycle and an odd cycle;
• using a current source to output a first current;
• establishing a four-phase sequential and cyclical timing scheme comprising a first phase, a second phase, a third phase, and a fourth phase in accordance with a state of the clock and a state of a cycle signal that toggles upon a cycle transition;
• steering the first current onto a first capacitor and enabling charge sharing between a second capacitor and a fourth capacitor during the first phase;
• steering the first current onto the second capacitor and enabling charge sharing between the first capacitor and a third capacitor during the second phase;
• discharging the first capacitor and enabling charge sharing between the second capacitor and the fourth capacitor during the third phase;
• and
• discharging the second capacitor and enabling charge sharing between the first capacitor and the third capacitor during the fourth phase.