# US 2025/0149484 A1 · Semiconductor device including bumps and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0149484 A1 - Document ID: US20250149484A1 - Status: Published application - Kind: A1 - Application number: 18/601,215 - Filed: 2024-03-11 - Published: 2025-05-08 - Earliest claimed: 2023-11-02 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Hyun Chul SEO - Web page: https://patentgrep.com/patent/US20250149484A1 ## CPC - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/90: Bond pads, in general - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/07236: {Soldering or alloying} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device including bumps and a method of manufacturing the same. The semiconductor device includes a first pillar and a second pillar formed over a substrate, a first solder layer configured to cover a first surface of the first pillar, and a second solder layer configured to cover a second surface of the second pillar. The first surface of the first pillar has a lower height than a height of the second surface of the second pillar. The second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface. ## Claims ### Claim 1 A semiconductor device comprising: a first pillar and a second pillar formed over a substrate; a first solder layer configured to cover a first surface of the first pillar; and a second solder layer configured to cover a second surface of the second pillar; wherein the first surface of the first pillar has a lower height than a height of the second surface of the second pillar and the second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface, wherein the first surface of the first pillar is a surface of the first pillar at a farthest distance from a surface of the substrate, and the second surface of the second pillar is a surface of the second pillar at a farthest distance from the surface the substrate. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein: a first height of the first surface of the first pillar is a first distance from a surface of the substrate, and a second height of the second surface of the second pillar is a second distance from the surface of the substrate, and a first thickness of the first solder layer is a distance from the first surface to a first end of the first solder layer, and a second thickness of the second solder layer is a distance from the second surface to a second end of the second solder layer, wherein the first end of the first solder layer is an end of the first solder layer farthest from the first pillar, and the second end of the second solder layer is an end of the second solder layer farthest from the second pillar. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the substrate comprises a conductive pad connected to the first pillar. ### Claim 4 (depends on 3) The semiconductor device of claim 3, further comprising, on the substrate, a dielectric layer that exposes the conductive pad, wherein the second pillar is disposed on the dielectric layer such that the second surface of the second pillar has a height greater than a height of the first surface of the first pillar by a thickness of the dielectric layer. ### Claim 5 (depends on 4) The semiconductor device of claim 4, further comprising: a first underlying layer formed between the first pillar and the conductive pad; and a second underlying layer formed between the second pillar and the dielectric layer. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the second pillar has a thickness identical to a thickness of the first pillar or has a thickness greater than the thickness of the first pillar. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the second pillar has a width identical to a width of the first pillar or has a width greater than the width of the first pillar. ### Claim 8 A semiconductor device comprising: a first substrate; a second substrate that is disposed over the first substrate and that comprises a first conductive trace and a second conductive trace; a first pillar and a second pillar disposed between the first substrate and the second substrate; a first solder layer configured to cover a first surface of the first pillar; and a second solder layer configured to cover a second surface of the second pillar; wherein the first surface of the first pillar has a lower height than a height of the second surface of the second pillar, wherein the first surface of the first pillar is a surface of the first pillar at a farthest distance from a surface of the substrate, and the second surface of the second pillar is a surface of the second pillar at a farthest distance from the surface the substrate; wherein the first solder layer is connected to the first conductive trace; wherein the second solder layer is connected to the second conductive trace; and wherein a distance between the first surface and the first conductive trace is greater than a distance between the second surface and the second conductive trace. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first substrate comprises a conductive pad connected to the first pillar; wherein the semiconductor device further comprises, on the substrate, a dielectric layer that exposes the conductive pad; and wherein the second pillar is disposed on the dielectric layer such that the second surface of the second pillar has a height greater than a height of the first surface of the first pillar by a thickness of the dielectric layer. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the first substrate further comprises: conductive vias configured to support the conductive pad; conductive patterns connected to the conductive pad by the conductive vias; and an insulating layer configured to insulate the conductive vias and the conductive patterns; wherein the dielectric layer comprises: a first dielectric layer that exposes a section of the conductive pad and that comprises an inorganic insulating layer; and a second dielectric layer that is disposed on the first dielectric layer and that comprises a carbon polymer insulating layer. ### Claim 11 A method of manufacturing a semiconductor device, comprising: forming a first pillar and a second pillar over a substrate; forming a first resist pattern comprising a first opening that exposes a first surface of the first pillar and comprising a second opening that exposes a second surface of the second pillar and that has a smaller width than the width of the first opening, wherein the first surface of the first pillar is a surface of the first pillar at a farthest distance from a surface of the substrate, and the second surface of the second pillar is a surface of the second pillar at a farthest distance from the surface the substrate; forming a first solder pattern within the first opening and a second solder pattern within the second opening; removing the first resist pattern; and forming a first solder layer by reflowing the first solder pattern and forming a second solder layer by reflowing the second solder pattern. ### Claim 12 (depends on 11) The method of claim 11, wherein the first pillar and the second pillar are formed such that the first surface of the first pillar has a lower height than the second surface of the second pillar. ### Claim 13 (depends on 12) The method of claim 12, wherein the second solder layer is formed having a smaller thickness than the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface. ### Claim 14 (depends on 11) The method of claim 11, wherein the second solder pattern is formed having a smaller volume than the first solder pattern due to a difference between a width of the first opening and a width of the second opening. ### Claim 15 (depends on 11) The method of claim 11, wherein: the substrate comprise a conductive pad, and the first pillar is connected to the conductive pad. ### Claim 16 (depends on 15) The method of claim 15, further comprising forming, over the substrate, a dielectric layer that exposes the conductive pad, wherein the second pillar is connected to the dielectric layer and formed such that the second surface of the second pillar has a height greater than a height of the first surface of the first pillar by a thickness of the dielectric layer. ### Claim 17 (depends on 16) The method of claim 16, wherein the forming the first pillar and the second pillar comprises: forming a seed layer for plating, which covers the conductive pad and extends to cover the dielectric layer; forming a second resist pattern comprising a third opening that overlaps the conductive pad and a fourth opening that overlaps the dielectric layer; and plating the first pillar within the first opening, and plating the second pillar within the fourth openings. ### Claim 18 (depends on 11) The method of claim 11, wherein the first solder pattern is formed by plating a solder material within the first opening, and the second solder pattern is formed by plating a solder material within the second opening. ### Claim 19 (depends on 11) The method of claim 11, wherein the second pillar is formed having a thickness identical to a thickness of the first pillar or having a greater thickness than the thickness of the first pillar. ### Claim 20 (depends on 11) The method of claim 11, wherein the second pillar is formed having a width identical to a width of the first pillar or having a greater width than the width of the first pillar. ### Claim 21 A semiconductor device comprising: a first pillar and a second pillar formed over a substrate; a first solder layer configured to cover a first surface of the first pillar; and a second solder layer configured to cover a second surface of the second pillar; wherein the second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface.