# US 2025/0149461 A1 · Multi-device graded embedding package substrate and manufacturing method thereof

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- Number: US 2025/0149461 A1
- Document ID: US20250149461A1
- Status: Published application
- Kind: A1
- Application number: 19/011,763
- Filed: 2025-01-07
- Published: 2025-05-08
- Earliest claimed: 2021-05-14
- Assignees: Zhuhai ACCESS Semiconductor Co., Ltd.
- Applicants: Zhuhai ACCESS Semiconductor Co., Ltd.
- Inventors: XIANMING CHEN; LEI FENG; BENXIA HUANG; YEJIE HONG
- Web page: https://patentgrep.com/patent/US20250149461A1

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K 3/4661: {Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387)}
- H10P 72/7426: {used as a support during build up manufacturing of active devices}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/0198: {batch processes}
- H10W 72/9413: {on encapsulations}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

## Claims

### Claim 1

A multi-device graded embedding package substrate, comprising:
a first dielectric layer comprising a first conductive copper pillar layer penetrating through the first dielectric layer along a height direction and a first device cavity;
a second dielectric layer above the first dielectric layer, the second dielectric layer comprising a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer which are provided on the first wiring layer;
a third dielectric layer below the first dielectric layer, the third dielectric layer comprising a second wiring layer located in an upper surface of the third dielectric layer, a third conductive copper pillar layer provided on the second wiring layer,
a first device attached to a bottom of the first device cavity so that a terminal of the first device is conductively connected to the second wiring layer, the first device connected to the heat dissipation copper block layer via the first wiring layer;
a second device cavity penetrating through the first dielectric layer, the second dielectric layer and the third dielectric layer; and
a second device is attached to the bottom of the second device cavity, the second device having a thickness difference from the first device,
wherein the first wiring layer and the second wiring layer are conductively connected via the first conductive copper pillar layer.

### Claim 2 (depends on 1)

The multi-device graded embedding package substrate according to claim 1, wherein a third wiring layer is provided on the second dielectric layer, and a fourth wiring layer is provided on the third dielectric layer, wherein the first wiring layer and the third wiring layer are conductively connected via the second conductive copper pillar layer and the heat dissipation copper block layer, the second wiring layer and the fourth wiring layer are conductively connected via the third conductive copper pillar layer, the terminal of the second device is conductively connected to the fourth wiring layer, and a back surface of the second device is connected to the third wiring layer.

### Claim 3 (depends on 1)

The multi-device graded embedding package substrate according to claim 1, wherein a first packaging layer is further provided on the upper surface of the first dielectric layer and in a gap between the first device and the first device cavity, and a second packaging layer is further provided on the upper surface of the second dielectric layer and in a gap between the second device and the second device cavity.

### Claim 4 (depends on 1)

The multi-device graded embedding package substrate according to claim 1, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer comprise an organic dielectric material, an inorganic dielectric material, or a combination thereof.

### Claim 5 (depends on 4)

The multi-device graded embedding package substrate according to claim 4, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer comprise polyimide, epoxy, bismaleimide triazine resin, ceramic packing, fiberglass, or a combination thereof.

### Claim 6 (depends on 2)

The multi-device graded embedding package substrate according to claim 2, wherein the first device and the second device respectively comprise a device having a double-side terminal so that the terminal of one side of the first device is in conductive connection with the second wiring layer, the terminal of the other side of the first device is in conductive connection with the heat dissipation copper block layer through the first wiring layer, the terminal of one side of the second device is in conductive connection with the fourth wiring layer, and the terminal of the other side of the second device is in conductive connection with the third wiring layer.

### Claim 7 (depends on 2)

The multi-device graded embedding package substrate according to claim 2, wherein the first device and the second device comprise a device having a single-side terminal respectively so that the terminal of the first device is in conductive connection with the second wiring layer, a back surface of the first device is connected to the heat dissipation copper block layer through the first wiring layer, the terminal of the second device is in conductive connection with the fourth wiring layer, and the back surface of the second device is connected to the third wiring layer.

### Claim 8 (depends on 1)

The multi-device graded embedding package substrate according to claim 1, wherein the first device and the second device comprise at least one device respectively.

### Claim 9 (depends on 1)

The multi-device graded embedding package substrate according to claim 1, wherein the first device and the second device comprise one or more of a chip, a capacitor, an inductor, and a resistor respectively.

### Claim 10 (depends on 1)

The multi-device graded embedding package substrate according to claim 1, wherein the first conductive copper pillar layer, the second conductive copper pillar layer, the third conductive copper pillar layer comprise at least one copper through-hole pillar respectively.

### Claim 11 (depends on 10)

The multi-device graded embedding package substrate according to claim 10, wherein the first conductive copper pillar layer, the second conductive copper pillar layer, and the third conductive copper pillar layer comprise copper through-hole pillars of different dimensions respectively.