# US 2025/0149418 A1 · Semiconductor package and method of fabricating the same

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- Number: US 2025/0149418 A1
- Document ID: US20250149418A1
- Status: Published application
- Kind: A1
- Application number: 19/013,244
- Filed: 2025-01-08
- Published: 2025-05-08
- Earliest claimed: 2021-03-23
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jongyoun KIM; Minjun BAE; Hyeonseok LEE; Gwangjae JEON
- Web page: https://patentgrep.com/patent/US20250149418A1

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

## Claims

### Claim 1

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern in contact with the solder terminal;
a first dielectric layer on a sidewall of the under-bump pattern;
a redistribution pattern on the under-bump pattern; and
a redistribution seed pattern disposed between the redistribution pattern and the under-bump pattern, and
wherein:
the top surface of the under-bump pattern includes a first part and a second part connected to the first part;
a level of the second part is higher than a level of the bottom surface of the redistribution seed pattern; and
an angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the first part is in contact with the bottom surface of the redistribution seed pattern.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the first part is vertically overlapping the solder terminal.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, further comprising a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is in contact with the second part.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the level of the bottom surface of the second dielectric layer is higher than the level of the first part.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, further comprising an under-bump seed pattern between the first dielectric layer and the sidewall of the under-bump pattern, the under-bump seed pattern exposing a bottom surface of the under-bump pattern.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein a level of the top surface of the under-bump seed pattern is lower than the level of the second part.

### Claim 8 (depends on 6)

The semiconductor package of claim 6, wherein a level of the top surface of the under-bump seed pattern is higher than the level of the second part.

### Claim 9 (depends on 6)

The semiconductor package of claim 6, wherein the under-bump seed pattern does not extend onto any of a top surface of the first dielectric layer and the bottom surface of the under-bump pattern.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, further comprising:
a molding layer covering the semiconductor chip on the top surface of the redistribution pattern;
an upper redistribution layer on the molding layer; and
an upper package on the upper redistribution layer,
wherein the upper package includes an upper substrate; and
an upper semiconductor chip on the upper substrate.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, further comprising:
a connection substrate disposed between the redistribution pattern and the upper redistribution layer,
wherein the connection substrate includes a substrate hole and a conductive structure, and
wherein the semiconductor chip is disposed in the substrate hole.

### Claim 12

A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip and a chip stack arranged to be spaced apart from each other in a horizontal direction on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern in contact with the solder terminal;
a dielectric layer on a sidewall of the under-bump pattern;
a redistribution pattern on the under-bump pattern; and
a redistribution seed pattern disposed between the redistribution pattern and the under-bump pattern,
wherein the top surface of the under-bump pattern has a downwardly convex shape, and
wherein a level of the bottom surface of the redistribution seed pattern is lower than the top surface of the dielectric layer.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, further comprising:
a package substrate disposed below the redistribution substrate, wherein the solder terminal is disposed between the redistribution substrate and the package substrate.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein the level of the bottom surface of the redistribution seed pattern is lower than the level of the uppermost portion of the top surface of the under-bump pattern.

### Claim 15 (depends on 12)

The semiconductor package of claim 12, further comprising:
an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, the under-bump seed pattern exposing a bottom surface of the under-bump pattern.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the level of the bottom surface of the redistribution seed pattern is disposed between the level of the bottom surface of the under-bump seed pattern and the top surface of the under-bump seed pattern.

### Claim 17 (depends on 15)

The semiconductor package of claim 15, wherein a level of the uppermost portion of the top surface of the under-bump pattern is same as the level of the top surface of the under-bump seed pattern.