DRAM with Analog Refresh Loop
AssigneeMixed Signal Machines Ltd.
InventorsBnaya Ben Nun, Amir Shimon
Life of this patent
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Abstract
A Dynamic Random-Access Memory (DRAM) device includes a plurality of DRAM cells, a control circuit and an analog Arithmetic-Logic Unit (aALU). The DRAM cells include respective storage capacitors configured to be charged to respective voltages. The control circuit is configured to read a voltage from a target DRAM cell and to refresh the target DRAM cell using a refresh voltage that is derived from the read voltage. The aALU is configured to derive the refresh voltage from the read voltage such that the refresh voltage approximates a voltage previously written to the target DRAM cell, by performing analog operations.
Claims19
A Dynamic Random-Access Memory (DRAM) device, comprising:
- a plurality of DRAM cells comprising respective storage capacitors configured to be charged to respective voltages;
- a control circuit, configured to read a voltage from a target DRAM cell and to refresh the target DRAM cell using a refresh voltage that is derived from the read voltage;
- and
- an analog Arithmetic-Logic Unit (aALU), configured to derive the refresh voltage from the read voltage such that the refresh voltage approximates a voltage previously written to the target DRAM cell, by performing analog operations.
An analog Dynamic Random-Access Memory (analog-DRAM) device, comprising a plurality of storage capacitors that are configured to store a continuous range of an electric charge, representing a continuously defined analog value.
A method, comprising:
- operating a plurality of Dynamic Random-Access Memory (DRAM) cells comprising respective storage capacitors configured to be charged to respective voltages;
- using a control circuit, reading a voltage from a target DRAM cell and refreshing the target DRAM cell using a refresh voltage that is derived from the read voltage;
- and
- using an analog Arithmetic-Logic Unit (aALU), deriving the refresh voltage from the read voltage such that the refresh voltage approximates a voltage previously written to the target DRAM cell, by performing analog operations.
Dependencies are inferred from the claim text.