# US 2025/0147893 A1 · Cache evict duplication management

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- Number: US 2025/0147893 A1
- Document ID: US20250147893A1
- Status: Published application
- Kind: A1
- Application number: 18/937,091
- Filed: 2024-11-05
- Published: 2025-05-08
- Earliest claimed: 2023-11-06
- Assignees: Akeana, Inc.
- Applicants: Akeana, Inc.
- Inventors: Sanjay Patel
- Web page: https://patentgrep.com/patent/US20250147893A1

## CPC

- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 13/1673: {using buffers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques for coherent processor cache control are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a shared local cache, and the plurality of processor cores implements special cache coherency operations. An evict buffer is coupled to the plurality of processor cores. The evict buffer is shared among the plurality of processor cores, and the evict buffer enables delayed writes. Evict buffer writes are monitored. The monitoring evict buffer writes identifies a special cache coherency operation. The special cache coherency operation that was identified comprises a global snoop operation. The global snoop operation is initiated from a non-local agent within a globally coherent system. An evict buffer entry is marked. The marking corresponds to the special cache coherency operation that was identified, and the marking enables management of cache evict duplication.

## Claims

### Claim 1

A processor-implemented method for cache management comprising:
accessing a plurality of processor cores, wherein each processor of the plurality of processor cores includes a shared local cache, and wherein the plurality of processor cores implements special cache coherency operations;
coupling an evict buffer to the plurality of processor cores, wherein the evict buffer is shared among the plurality of processor cores, and wherein the evict buffer enables delayed writes;
monitoring evict buffer writes, wherein the monitoring evict buffer writes identifies a special cache coherency operation; and
marking an evict buffer entry, wherein the marking corresponds to the special cache coherency operation that was identified, and wherein the marking enables management of cache evict duplication.

### Claim 2 (depends on 1)

The method of claim 1 wherein the special cache coherency operation that was identified comprises a global snoop operation.

### Claim 3 (depends on 2)

The method of claim 2 wherein the global snoop operation is initiated from an agent within a globally coherent system.

### Claim 4 (depends on 1)

The method of claim 1 wherein the special cache coherency operation that was identified comprises a cache maintenance operation (CMO).

### Claim 5 (depends on 4)

The method of claim 4 wherein the CMO comprises a cache block operation (CBO) CLEAN instruction.

### Claim 6 (depends on 1)

The method of claim 1 wherein the special cache coherency operation that was identified causes dirty data to be written into the evict buffer.

### Claim 7 (depends on 1)

The method of claim 1 further comprising receiving an additional evict buffer write by the evict buffer.

### Claim 8 (depends on 7)

The method of claim 7 further comprising performing a fast compare between the additional evict buffer write and the evict buffer entry that was marked to detect duplication.

### Claim 9 (depends on 8)

The method of claim 8 wherein the comparing is based on a partial address of the evict buffer entry.

### Claim 10 (depends on 9)

The method of claim 9 wherein the partial address comprises a cache set index.

### Claim 11 (depends on 8)

The method of claim 8 further comprising sending the operation that caused the additional evict buffer write to a replay buffer, based on a duplication match in the fast compare.

### Claim 12 (depends on 11)

The method of claim 11 further comprising performing a full compare between the additional evict buffer write with the evict buffer entry that was marked.

### Claim 13 (depends on 12)

The method of claim 12 wherein logic for the fast compare and the full compare comprises shared logic.

### Claim 14 (depends on 12)

The method of claim 12 further comprising marking, in the replay buffer, the operation that caused the additional evict buffer write, based on a duplication mismatch in the full compare.

### Claim 15 (depends on 14)

The method of claim 14 further comprising replaying the operation that caused the additional evict buffer write, based on the duplication mismatch marking and a re-presentation of the operation that caused the additional evict buffer write from the replay buffer.

### Claim 16 (depends on 15)

The method of claim 15 wherein the re-presentation by the replay buffer forces an override of a subsequent fast compare.

### Claim 17 (depends on 1)

The method of claim 1 wherein the shared local cache is coupled to a grouping of two or more processor cores of the plurality of processor cores.

### Claim 18 (depends on 17)

The method of claim 17 wherein the shared local cache is shared among the two or more processor cores.

### Claim 19 (depends on 18)

The method of claim 18 wherein the grouping of two or more processor cores and the shared local cache operates using local coherency.

### Claim 20 (depends on 19)

The method of claim 19 wherein the local coherency is distinct from a global coherency.

### Claim 21 (depends on 20)

The method of claim 20 further comprising performing a cache maintenance operation in the grouping of two or more processor cores and the shared local cache.

### Claim 22 (depends on 21)

The method of claim 21 wherein the cache maintenance operation generates cache coherency transactions between the global coherency and the local coherency.

### Claim 23 (depends on 20)

The method of claim 20 further comprising performing a global snoop operation on the shared local cache.

### Claim 24

A computer program product embodied in a non-transitory computer readable medium for cache management, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:
accessing a plurality of processor cores, wherein each processor of the plurality of processor cores includes a shared local cache, and wherein the plurality of processor cores implements special cache coherency operations;
coupling an evict buffer to the plurality of processor cores, wherein the evict buffer is shared among the plurality of processor cores, and wherein the evict buffer enables delayed writes;
monitoring evict buffer writes, wherein the monitoring evict buffer writes identifies a special cache coherency operation; and
marking an evict buffer entry, wherein the marking corresponds to the special cache coherency operation that was identified, and wherein the marking enables management of cache evict duplication.

### Claim 25

A computer system for cache management comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
access a plurality of processor cores, wherein each processor of the plurality of processor cores includes a shared local cache, and wherein the plurality of processor cores implements special cache coherency operations;
couple an evict buffer to the plurality of processor cores, wherein the evict buffer is shared among the plurality of processor cores, and wherein the evict buffer enables delayed writes;
monitor evict buffer writes, wherein the monitoring evict buffer writes identifies a special cache coherency operation; and
mark an evict buffer entry, wherein the marking corresponds to the special cache coherency operation that was identified, and wherein the marking enables management of cache evict duplication.