# US 2025/0147764 A1 · Processor identification > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0147764 A1 - Document ID: US20250147764A1 - Status: Published application - Kind: A1 - Application number: 18/913,223 - Filed: 2024-10-11 - Published: 2025-05-08 - Earliest claimed: 2023-11-03 - Assignees: STMicroelectronics International N.V. - Applicants: STMicroelectronics International N.V. - Inventors: Philippe Pijourlet; Brice Dufour - Web page: https://patentgrep.com/patent/US20250147764A1 ## CPC - G06F 9/35: Indirect addressing - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present description concerns a device comprising a bus, peripherals coupled to the bus, the peripherals comprising a first circuit, processors coupled to the bus and initiating accesses to the peripherals, each comprising an address phase followed by a data phase, and for each processor, a second circuit delivering an identifier of the processor over the bus during the address phase of each access initiated by the processor. For each read access to the first circuit initiated by one of the processors, the first circuit stores the identifier present over the bus during the address phase of the access, and then delivers the identifier stored over the bus during the data phase of the access. ## Claims ### Claim 1 A device comprising: a bus; processors coupled to the bus, and configured to execute a same instruction set and initiate accesses to peripherals via the bus, each access comprising an address phase followed by a data phase; for each processor, a second circuit associated with the processor and configured to provide an identifier of the processor on the bus during the address phase of each access initiated by the processor; and the peripherals, coupled to the bus, the peripherals comprising a first circuit configured to, at each read access to the first circuit initiated by one of the processors: store the identifier present on the bus during the address phase of the access; and provide the bus with the stored identifier during the data phase of the access. ### Claim 2 (depends on 1) The device according to claim 1, wherein: the peripherals comprise a memory shared between at least two of the processors; and a program comprising a sequence of instructions of the instruction set is stored in the memory and is accessible to the at least two of the processors. ### Claim 3 (depends on 2) The device according to claim 2, wherein the program comprises at least one portion an execution of which is conditioned by the identifier of the processor executing the program. ### Claim 4 (depends on 1) The device according to claim 1, wherein, for each access by one of the processors to one of the peripherals other than the first circuit, the device is configured to condition access to the peripheral based on the identifier of the processor having initiated the access. ### Claim 5 (depends on 1) The device according to claim 1, wherein the first circuit comprises a register configured to: store, during the address phase of each read access to the first circuit, the identifier present on the bus and corresponding to the processor having initiated the read access; and provide the bus with, during the data phase of each read access to the first circuit, the identifier stored during the address phase of the read access. ### Claim 6 (depends on 1) The device according to claim 1, wherein each identifier corresponds to a different processor. ### Claim 7 (depends on 1) The device according to claim 1, wherein read and write accesses to the second circuits are impossible. ### Claim 8 (depends on 1) The device according to claim 1, wherein the bus is an advanced microcontroller bus architecture (AMBA)-type bus. ### Claim 9 (depends on 1) The device according to claim 1, wherein the identifier of each processor is hard-coded in the second circuit associated with the processor. ### Claim 10 (depends on 1) The device according to claim 1, wherein the first circuit is read-only accessible. ### Claim 11 A method implemented in a device comprising a bus, peripherals connected to the bus and comprising a first circuit, processors coupled to the bus, executing a same instruction set, each being associated with a second circuit and initiating accesses to the peripherals via the bus, each access comprising an address phase followed by a data phase, the method comprising: initiating, by one of the processors, a read access to the first circuit; providing the bus with, during the address phase of the access and with the second circuit associated with the processor initiating the access, an identifier of the processor; storing, by the first circuit, the identifier present on the bus during the address phase of the access; and providing, by the first circuit during the data phase of the access, the bus with the stored identifier. ### Claim 12 (depends on 11) The method according to claim 11, wherein: the peripherals comprise a memory shared between at least two of the processors; and a program comprising a sequence of instructions of the instruction set is stored in the memory and is accessible to the at least two of the processors. ### Claim 13 (depends on 12) The method according to claim 12, wherein the program comprises at least one portion an execution of which is conditioned by the identifier of the processor executing the program. ### Claim 14 (depends on 11) The method according to claim 11, wherein, for each access by one of the processors to one of the peripherals other than the first circuit, the device is configured to condition access to the peripheral based on the identifier of the processor having initiated the access. ### Claim 15 (depends on 11) The method according to claim 11, wherein the first circuit comprises a register configured to: store, during the address phase of each read access to the first circuit, the identifier present on the bus and corresponding to the processor having initiated the read access; and provide the bus with, during the data phase of each read access to the first circuit, the identifier stored during the address phase of the read access. ### Claim 16 (depends on 11) The method according to claim 11, wherein each identifier corresponds to a different processor. ### Claim 17 (depends on 11) The method according to claim 11, wherein read and write accesses to the second circuits are impossible. ### Claim 18 (depends on 11) The method according to claim 11, wherein the bus is an advanced microcontroller bus architecture (AMBA)-type bus. ### Claim 19 (depends on 11) The method according to claim 11, wherein the identifier of each processor is hard-coded in the second circuit associated with the processor. ### Claim 20 (depends on 11) The method according to claim 11, wherein the first circuit is read-only accessible.