Multiplier and its computational processing method
AssigneeGlenfly Tech Co., Ltd. (Shanghai)
InventorsYaohui ZENG, Yuqin Yu, Renyu Bian, Huaisheng Zhang
Life of this patent
Estimating the term…
Loading patent…
AssigneeGlenfly Tech Co., Ltd. (Shanghai)
InventorsYaohui ZENG, Yuqin Yu, Renyu Bian, Huaisheng Zhang
Estimating the term…
According to an aspect of the disclosure, a computational processing method of multiplier, performed by a processor chip, includes: obtaining, based on n first operands a[k], a first operating part A including BIT(A) bits; obtaining x first encoded data Enc[m] by assigning a lowest bit of consecutive three-bit numbers spanning two adjacent first operands a[k] and a[k−1] to 0, and performing Booth-encoding on the first operating part A; obtaining, based on n second operands b[k], n corresponding second operating parts B[k], each of which has BIT(B) bits; obtaining x partial products based on multiplying the x first encoded data Enc[m] with the n corresponding second operating parts; obtaining an accumulation result based on accumulating the x partial products; obtaining a multiplication result based on truncating the accumulation result; wherein, n, k, x, and m are integers, and wherein 0≤k<n, and 0≤m<x.
A computational processing method of multiplier, performed by a processor chip, comprising:
A multiplier of a processor chip, comprising:
A processor chip comprising a multiplier, wherein the multiplier comprises:
Dependencies are inferred from the claim text.