# US 2025/0147702 A1 · Nonvolatile semiconductor memory

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- Number: US 2025/0147702 A1
- Document ID: US20250147702A1
- Status: Published application
- Kind: A1
- Application number: 19/018,307
- Filed: 2025-01-13
- Published: 2025-05-08
- Earliest claimed: 2019-06-19
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Hiroshi MAEJIMA
- Web page: https://patentgrep.com/patent/US20250147702A1

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06N 3/0499: Feedforward networks
- G06N 3/08: Learning methods
- G06N 3/09: Supervised learning
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C 2211/5644: Multilevel memory comprising counting devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile semiconductor memory includes a first memory string, a first interconnect coupled to one end of the first memory string, a second interconnect coupled to another end of the first memory string, a first circuit configured to control the first interconnect in accordance with first data, and a second circuit coupled to the second interconnect, the second circuit including a current mirror circuit, and the second circuit being configured to output second data based on an amount of a current flowing through the second interconnect.

## Claims

### Claim 1

A nonvolatile semiconductor memory, comprising:
a first memory string;
a first interconnect coupled to one end of the first memory string;
a second interconnect coupled to another end of the first memory string;
a first circuit configured to control the first interconnect in accordance with first data; and
a second circuit coupled to the second interconnect, the second circuit including a current mirror circuit, and the second circuit being configured to output second data based on an amount of a current flowing through the second interconnect.

### Claim 2 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein the first memory string includes a plurality of memory cells coupled in series.

### Claim 3 (depends on 2)

The nonvolatile semiconductor memory according to claim 2, wherein the first memory string further includes a first select transistor between the first interconnect and the plurality of memory cells and a second select transistor between the second interconnect and the plurality of memory cells.

### Claim 4 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, further comprising:
a second memory string coupled, at one end, to the second interconnect;
a third interconnect coupled to another end of the second memory string; and
a fourth interconnect commonly coupled to a first transistor included in the first memory string and a second transistor included in the second memory string.

### Claim 5 (depends on 4)

The nonvolatile semiconductor memory according to claim 4, wherein:
a voltage is applied to the fourth interconnect in accordance with the first data, and
the first circuit is configured to control the first interconnect and the third interconnect.

### Claim 6 (depends on 4)

The nonvolatile semiconductor memory according to claim 4, wherein the fourth interconnect is a word line.

### Claim 7 (depends on 4)

The nonvolatile semiconductor memory according to claim 4, wherein:
the first circuit is configured to perform a first read operation of applying a first voltage to the fourth interconnect, and a second read operation of applying a second voltage higher than the first voltage to the fourth interconnect, the second read operation being performed after the first read operation,
the first interconnect is precharged to a third voltage prior to the first read operation, and
the first interconnect is not precharged in the second read operation in a case where the first interconnect has changed to a fourth voltage lower than the third voltage as a result of the first read operation.

### Claim 8 (depends on 7)

The nonvolatile semiconductor memory according to claim 7, wherein:
the third interconnect is precharged to the third voltage prior to the first read operation, and
the third interconnect is precharged in the second read operation in a case where the third interconnect has not changed to the fourth voltage as a result of the first read operation.

### Claim 9 (depends on 4)

The nonvolatile semiconductor memory according to claim 4, wherein a fifth voltage is applied to the first interconnect and a sixth voltage different from the fifth voltage is applied to the third interconnect in accordance with the first data.

### Claim 10 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein the second data is a digital value into which the amount of the current has been converted.

### Claim 11 (depends on 10)

The nonvolatile semiconductor memory according to claim 10, wherein the digital value is obtained by binary search conversion.

### Claim 12 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein a first memory cell included in the first memory string is a NAND flash memory.

### Claim 13 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein:
the first interconnect is a bit line, and
the second interconnect is a source line.

### Claim 14 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein the second circuit includes a comparator including a first terminal to which a first voltage based on the amount of the current is input and a second terminal to which a second voltage is input.

### Claim 15 (depends on 14)

The nonvolatile semiconductor memory according to claim 14, wherein the second data is output from the comparator.

### Claim 16 (depends on 14)

The nonvolatile semiconductor memory according to claim 14, wherein the second circuit further includes:
a third transistor coupled, at one end and a gate, to the first terminal; and
a fourth transistor coupled, at one end, to the second terminal, and coupled, at a gate, to the gate of the third transistor.

### Claim 17 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein the second circuit includes a diode coupling.

### Claim 18 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein:
the current mirror circuit includes a fifth transistor and a sixth transistor,
the fifth transistor is coupled, at a gate, to a gate of the sixth transistor, and
a width of the gate of the sixth transistor is different from a width of the gate of the fifth transistor.

### Claim 19 (depends on 18)

The nonvolatile semiconductor memory according to claim 18, wherein:
the fifth transistor is coupled, at one end, to the second interconnect, and
the amount of the current is copied by the current mirror circuit.

### Claim 20 (depends on 1)

The nonvolatile semiconductor memory according to claim 1, wherein the second circuit includes:
a third circuit including a comparator including a first terminal to which a reference voltage is input and a second terminal coupled to the second interconnect; and
a fourth circuit configured to convert the amount of the current into a digital value.