# US 2025/0147697 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0147697 A1 - Document ID: US20250147697A1 - Status: Published application - Kind: A1 - Application number: 19/013,007 - Filed: 2025-01-08 - Published: 2025-05-08 - Earliest claimed: 2021-03-30 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Akio SUGAHARA; Zhao LU; Takehisa KUROSAWA; Yuji NAGAI - Web page: https://patentgrep.com/patent/US20250147697A1 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 7/1045: {Read-write mode select circuits} - G11C 7/109: {Control signal input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 2207/105: Aspects related to pads, pins or terminals - G11C 2207/107: Serial-parallel conversion of data or prefetch - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad. ## Claims ### Claim 1 A memory system comprising: a semiconductor memory device, and a memory controller, wherein the semiconductor memory device comprises: a first pad; a second pad; a first memory string comprising a plurality of first memory cell transistors connected in series; a first bit line connected to one end of the first memory string; a first source line connected to the other end of the first memory string; a plurality of first word lines connected to gates of the first memory cell transistors, respectively; a first sense amplifier connected to the first bit line; and a first data register connected to the first sense amplifier and configured to store data read from one of the first memory cell transistors, wherein when the memory controller sends a first command to the second pad of the semiconductor memory device, the semiconductor memory device outputs the data stored in the first data register toward the memory controller from the first pad, and when the memory controller sends a second command to the second pad of the semiconductor memory device, the semiconductor memory device outputs status information toward the memory controller from the second pad. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the semiconductor memory device further comprises: a first driver connected to the first pad; a first receiver connected to the first pad; a second driver connected to the second pad; and a second receiver connected to the second pad. ### Claim 3 (depends on 2) The memory system according to claim 2, wherein, in the semiconductor memory device, the first driver is activated when the semiconductor memory device outputs the data stored in the first data register toward the memory controller from the first pad, and the second driver is activated and the first driver is not activated when the semiconductor memory device outputs the status information toward the memory controller from the second pad. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the semiconductor memory device further comprises: a command register configured to store command information; an address register configured to store address information; and a status register configured to store the status information, and in response to the second command, the semiconductor memory device outputs the status information stored in the status register toward the memory controller from the second pad. ### Claim 5 (depends on 4) The memory system according to claim 4, wherein when the memory controller sends a third command instructing a read operation targeting one of the first memory cell transistors to the second pad of the semiconductor memory device, the command register stores the command information indicating the read operation, the address register stores the address information indicating the one of the first memory cell transistors, and the status register stores the status information indicating whether the read operation is being performed or finished. ### Claim 6 (depends on 5) The memory system according to claim 5, wherein in the semiconductor memory device, the status information stored in the status register is updated in accordance with progress of the read operation. ### Claim 7 (depends on 2) The memory system according to claim 2, wherein, in the semiconductor memory device, n first pads are provided, n being an integer of 8 or multiple thereof, and n first drivers and n first receivers are provided correspondingly with the n first pads. ### Claim 8 (depends on 7) The memory system according to claim 7, wherein in the semiconductor memory device, the second pad is different from any one of the n first pads. ### Claim 9 (depends on 7) The memory system according to claim 7, wherein in the semiconductor memory device, the second driver is activated regardless of whether the first driver is activated or not. ### Claim 10 (depends on 1) The memory system according to claim 1, wherein the semiconductor memory device further comprises: a second memory string comprising a plurality of second memory cell transistors connected in series, one end of the second memory string being connected to the first bit line, the other end of the second memory string being connected to the first source line; and a plurality of second word lines connected to gates of the second memory cell transistors, respectively. ### Claim 11 (depends on 4) The memory system according to claim 4, wherein the semiconductor memory device further comprises: a feature register configured to store feature information. ### Claim 12 (depends on 11) The memory system according to claim 11, wherein when the memory controller sends a fourth command instructing a set feature operation to the second pad of the semiconductor memory device, the feature register of the semiconductor memory device stores the feature information included in the fourth command. ### Claim 13 (depends on 11) The memory system according to claim 11, wherein when the memory controller sends a fifth command instructing a get feature operation to the second pad of the semiconductor memory device, the semiconductor memory device outputs the feature information stored in the feature register toward the memory controller from the second pad. ### Claim 14 (depends on 1) The memory system according to claim 1, wherein the semiconductor memory device further comprises: a third pad; and a fourth pad, and after the memory controller sends the first command instructing the data output to the second pad of the semiconductor memory device, the memory controller toggles a first signal input to the third pad to cause the semiconductor memory device to output the data from the first pad. ### Claim 15 (depends on 14) The memory system according to claim 14, wherein after the memory controller sends the second command instructing the status output to the second pad of the semiconductor memory device, the memory controller toggles a second signal input to the fourth pad to cause the semiconductor memory device to output the status information from the second pad.