# US 2025/0147667 A1 · Memory device and its operating method, memory system and operating method thereof

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- Number: US 2025/0147667 A1
- Document ID: US20250147667A1
- Status: Published application
- Kind: A1
- Application number: 18/595,879
- Filed: 2024-03-05
- Published: 2025-05-08
- Earliest claimed: 2023-11-06
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Xingwei Tang; Guangchang Ye; Lu Guo
- Web page: https://patentgrep.com/patent/US20250147667A1

## CPC

- G06F 3/0613: {in relation to throughput}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.

## Claims

### Claim 1

A memory device, comprising:
an array of memory cells, including a plurality of memory cells, wherein a preset number of the plurality of memory cells form a code word;
a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes a number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;
adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage;
obtain a first result corresponding to at least one of the code words at the adjusted read voltage; and
determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the peripheral circuit is configured to:
read data stored in at least one of the code words at the target read voltage to obtain a second result;
perform a first adjustment to the target read voltage, and read data stored in at least one of the code words at the adjusted target read voltage to obtain a third result;
perform a logical operation on the second result and the third result to obtain a fourth result; and
count the number of bits in the fourth result that represent flip of bits in the third result relative to the second result to obtain a first result.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the peripheral circuit comprises:
a first latch configured to store the second result;
a second latch configured to store the third result; and
a third latch configured to store the fourth result.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the peripheral circuit is configured to:
when the first result corresponding to the target read voltage is less than or equal to a first preset value, perform a second adjustment to the target read voltage to obtain a target adjusted read voltage, wherein a step size of the second adjustment is greater than a step size of the first adjustment; and
obtain a first result corresponding to at least one of the code words at the target adjusted read voltage.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the peripheral circuit is configured to:
when the first result corresponding to at least one of the code words at the target adjusted read voltage is less than the first preset value and greater than a second preset value, continue to perform a second adjustment to the target adjusted read voltage, and obtain a first result corresponding to at least one of the code words at the adjusted read voltage, until a first result corresponding to a final adjusted read voltage is less than or equal to the second preset value; and
when the first result corresponding to the final adjusted read voltage is less than or equal to the second preset value, take the read voltage corresponding to the first result with the smallest count number among the first results as the valley voltage.

### Claim 6 (depends on 2)

The memory device of claim 2, wherein the peripheral circuit is configured to:
when the first result corresponding to the target read voltage is greater than a first preset value, perform multiple adjustments to the target read voltage, and obtain a plurality of first results respectively corresponding to at least one of the code words at the read voltages after multiple adjustments; and
when the plurality of first results are all greater than the first preset value, adjust the number of memory cells corresponding to at least one of the code words, wherein the number of memory cells corresponding to the code word after adjustment is less than the number of memory cells corresponding to the code word before adjustment.

### Claim 7 (depends on 4)

The memory device of claim 4, wherein the peripheral circuit is configured to:
obtain the first preset value, wherein the first preset value is equal to an upper limit of fail bit count supported by the memory device.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the peripheral circuit is configured to:
set a read mode of the memory device to a single level read mode before obtaining the first result corresponding to at least one of the code words at the target read voltage, wherein the single level read mode includes reading at least one bit of storage data stored in the memory cell with read voltages at one level.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein:
the memory cell includes M bits, the memory device includes M-type pages, and the memory cell with M bits reads its M bits of storage data with read voltages at N levels;
the M and N are both integers greater than 1, and N=2M−1; and
the peripheral circuit is configured to:
for read voltages at each level of the read voltages at multiple levels corresponding to each type of page, determine the valley voltage at each level in accordance with a plurality of first results corresponding to multiple read voltages at each level.

### Claim 10

A memory system, comprising:
one or more memory device, comprising:
an array of memory cells, including a plurality of memory cells, wherein a preset number of the plurality memory cells form a code word;
a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes the number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;
adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage;
obtain a first result corresponding to at least one of the code words at the adjusted read voltage; and
determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words; and
a memory controller coupled to the memory device and controlling the memory device.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein:
the memory controller is configured to:
send a first instruction before performing a read operation on data stored in the memory device, wherein the first instruction indicates to obtain the valley voltage;
the memory device is configured to:
receive the first instruction;
obtain the valley voltage; and
send the obtained valley voltage to the memory controller; and
the memory controller is further configured to:
perform a read operation on data stored in the memory device in accordance with the valley voltage; and
perform an error correction code decoding operation on a read result of the read operation.

### Claim 12

A method for operating a memory device, comprising:
obtaining a first result corresponding to at least one of code words at a target read voltage, wherein the first result includes a number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, wherein a difference between the first read voltage and the second read voltage is less than a preset voltage, and wherein the memory device includes an array of memory cells, the array of memory cells includes a plurality of memory cells, and a preset number of the plurality memory cells form a code word;
adjusting the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage;
obtaining a first result corresponding to at least one of the code words at the adjusted read voltage; and
determining a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words.

### Claim 13 (depends on 12)

The method of claim 12, wherein the obtaining the first result corresponding to at least one of code words at the target read voltage comprises:
reading data stored in at least one of the code words at the target read voltage to obtain a second result;
performing a first adjustment to the target read voltage, and reading data stored in at least one of the code words at the adjusted target read voltage to obtain a third result;
performing a logical operation on the second result and the third result to obtain a fourth result; and
counting the number of bits in the fourth result that represent flip of bits in the third result relative to the second result to obtain a first result.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
storing the second result in a first latch of the memory device;
storing the third result in a second latch of the memory device; and
storing the fourth result in a third latch of the memory device.

### Claim 15 (depends on 13)

The method of claim 13, wherein the adjusting the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage comprises:
performing a second adjustment to the target read voltage to obtain a target adjusted read voltage when the first result corresponding to the target read voltage is less than or equal to a first preset value, wherein a step size of the second adjustment is greater than a step size of the first adjustment; and
obtaining a first result corresponding to at least one of the code words at the target adjusted read voltage.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
when the first result corresponding to at least one of the code words at the target adjusted read voltage is less than the first preset value and greater than a second preset value, continuing to perform a second adjustment to the target adjusted read voltage, and obtaining a first result corresponding to at least one of the code words at the adjusted read voltage, until a first result corresponding to a final adjusted read voltage is less than or equal to the second preset value;
wherein the determining the valley voltage in accordance with the plurality of the first results comprises:
when the first result corresponding to the final adjusted read voltage is less than or equal to the second preset value, taking the read voltage corresponding to the smallest first result among the first results as the valley voltage.

### Claim 17 (depends on 12)

The method of claim 12, further comprising:
when the first result corresponding to the target read voltage is greater than a first preset value, performing multiple adjustments to the target read voltage, and obtaining a plurality of first results respectively corresponding to at least one of the code words at the read voltages after multiple adjustments; and
when the plurality of first results are all greater than the first preset value, adjusting the number of memory cells corresponding to at least one of the code words, wherein the number of memory cells corresponding to the code word after adjustment is less than the number of memory cells corresponding to the code word before adjustment.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
obtaining the first preset value, wherein the first preset value is equal to an upper limit of fail bit count supported by the memory device.

### Claim 19 (depends on 14)

The method of claim 14, further comprising:
setting a read mode of the memory device to a single level read mode before obtaining the first result corresponding to at least one of the code words at the target read voltage, wherein the single level read mode includes reading at least one bit of storage data stored in the memory cell with read voltages at one level.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the memory cell includes M bits, the memory device includes M-type pages, and the memory cell with M bits reads its M bits of storage data with read voltages at N levels;
the M and N are both integers greater than 1, and N=2M−1; and
the method further comprising:
for read voltages at each level of the read voltages at multiple levels corresponding to each type of page, determining the valley voltage at each level in accordance with a plurality of first results corresponding to multiple read voltages at each level.