# US 2025/0147665 A1 · Systems, methods, and apparatus for accessing memory with die-to-die interfaces

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- Number: US 2025/0147665 A1
- Document ID: US20250147665A1
- Status: Published application
- Kind: A1
- Application number: 18/935,341
- Filed: 2024-11-01
- Published: 2025-05-08
- Earliest claimed: 2023-11-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Soon Ju KIM; Hyoun Kwon JEONG; Soogil JEONG
- Web page: https://patentgrep.com/patent/US20250147665A1

## CPC

- G06F 3/0611: {in relation to response time}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus may include a die including a memory interface, a die-to-die (D2D) circuit comprising a D2D interface, and an intermediate section connected between the memory interface and the D2D interface, wherein the intermediate section comprises a transaction converter. The intermediate section may be configured to transfer data through the D2D interface using a protocol. The D2D interface may be configured to transfer data using flow control. The D2D interface may be configured to transfer data using a raw format.

## Claims

### Claim 1

An apparatus comprising:
a die comprising:
a memory interface;
a die-to-die (D2D) circuit comprising a D2D interface; and
an intermediate section configured to transfer data using the memory interface and the D2D interface, wherein the intermediate section comprises a transaction converter.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the intermediate section comprises a memory controller.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the intermediate section comprises one or more compute resources.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the intermediate section is configured to transfer data using a protocol.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the D2D interface is configured to transfer data using flow control.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein:
the D2D interface comprises a D2D link interface; and
the transaction converter is configured to convert a memory transaction to the D2D link interface.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the D2D interface is configured to transfer data using a raw format.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein:
the D2D interface comprises a D2D phy interface; and
the transaction converter is configured to convert a memory transaction to the D2D phy interface.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the intermediate section is configured to pack data into a raw format.

### Claim 10 (depends on 1)

The apparatus of claim 1 wherein the D2D interface comprises a D2D link interface, and the intermediate section comprises:
a memory controller configured to access a memory device using the memory interface; and
a transaction converter connected to the memory controller using a protocol interface, wherein the transaction converter is configured to convert a memory transaction between the protocol interface and the D2D link interface.

### Claim 11 (depends on 1)

The apparatus of claim 1 wherein:
the D2D interface comprises a D2D link interface; and
the intermediate section comprises a transaction converter configured to convert a memory transaction between the memory interface and the D2D link interface.

### Claim 12 (depends on 1)

The apparatus of claim 1 wherein:
the D2D interface comprises a D2D phy interface; and
the intermediate section comprises a transaction converter configured to convert a memory transaction between the memory interface and the D2D phy interface.

### Claim 13 (depends on 1)

The apparatus of claim 1 wherein the D2D interface comprises a D2D link interface, and the intermediate section comprises:
a memory controller configured to access a memory device using the memory interface; and
a transaction converter connected to the memory controller using a protocol interface;
a compute resource connected to the transaction converter; and
a format converter connected to the compute resource and the D2D link interface;
wherein the transaction converter is configured to convert a memory transaction between the protocol interface and the compute resource; and
wherein the format converter is configured to convert one or more signals between the compute resource and the D2D link interface.

### Claim 14 (depends on 1)

The apparatus of claim 1 wherein the D2D interface comprises a D2D link interface, and the intermediate section comprises:
a transaction converter;
a compute resource connected to the transaction converter; and
a format converter connected to the compute resource and the D2D link interface;
wherein the transaction converter is configured to convert a memory transaction between the memory interface and the compute resource; and
wherein the format converter is configured to convert one or more signals between the compute resource and the D2D link interface.

### Claim 15 (depends on 1)

The apparatus of claim 1 wherein the D2D interface comprises a D2D phy interface, and the intermediate section comprises:
a transaction converter;
a compute resource connected to the transaction converter; and
a format converter connected to the compute resource and the D2D phy interface;
wherein the transaction converter is configured to convert a memory transaction between the memory interface and the compute resource; and
wherein the format converter is configured to convert one or more signals between the compute resource and the D2D phy interface.

### Claim 16

An apparatus comprising:
a die comprising:
a memory interface;
a die-to-die (D2D) circuit comprising a D2D interface; and
a transaction converter connected between the memory interface and the D2D interface.

### Claim 17 (depends on 16)

The apparatus of claim 16, further comprising a protocol layer connected between the memory interface and the D2D interface.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein the D2D circuit comprises a link layer configured to transfer data using flow control.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein the D2D circuit comprises a phy layer configured to transfer data using a raw format.

### Claim 20

A method comprising:
performing, at a die, using a memory interface, a memory transaction;
converting, at the die, the memory transaction to a form for a die-to-die (D2D) interface; and
transferring, using the D2D interface, data associated with the memory transaction.