Packet routing between memory devices and related apparatuses, methods, and memory systems

A method for interconnecting host devices and one or more memory devices, the host devices each including at least one interface to communicate packet requests over respective packetized links, the one or more memory devices each including at least one interface to receive and respond to the packet requests over the respective packetized links, the host devices each further including local memory comprising a cache for caching data read from memory of the one or more memory devices, the method comprising:

• receiving routing configuration information at devices of a routing system, the devices of the routing system interconnected in a routing topology, respective ones of the devices of the routing system comprising a switch and interfaces;
• routing packet requests and responses between the host devices and respective memory device destinations over the respective packetized links based on the routing configuration information;
• and
• conveying cache coherency traffic between the host devices over at least one of the respective packetized links.

An interconnect system comprising:

• host devices including a first host device and a second host device, the first host device including at least a first interface to communicate packet requests over a first packetized link, the first host device including a first local memory comprising a first cache, the second host device including at least a second interface to communicate packet requests over a second packetized link, the second host device including a second local memory comprising a second cache;
• a memory device including at least one interface to receive and respond to packet requests over the first packetized link and the second packetized link;
• and
• a device of a routing system, the device of the routing system to route the packet requests and responses between the host devices and respective memory device destinations, the device comprising a switch and interfaces,
• wherein the first host device is to communicate read and write requests in the packet requests over the first packetized link and to cache data read from memory of the memory device in the first cache of the first host device, and the second host device is to communicate read and write requests in the packet requests over the second packetized link and to cache data read from the memory of the memory device in the second cache of the second host device, and
• wherein the first host device and the second host device are to communicate cache coherency traffic to each other over another packetized link via the at least first interface and the at least second interface.