# US 2025/0147409 A1 · Method for manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0147409 A1 - Document ID: US20250147409A1 - Status: Published application - Kind: A1 - Application number: 18/773,908 - Filed: 2024-07-16 - Published: 2025-05-08 - Earliest claimed: 2023-11-02 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Woo-Yong JUNG; Joon Hyun KIM; Seung Yoon LEE; Jeong Jin LEE; Chan HWANG - Web page: https://patentgrep.com/patent/US20250147409A1 ## CPC - G03F 1/42: Alignment or registration features, e.g. alignment marks on the mask substrates - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract A method for manufacturing a semiconductor device includes providing a first pre-reticle including a first overlay mark and a first on-cell pattern. A second pre-reticle is provided that includes a second overlay mark and a second on-cell pattern. A first pattern is formed from the first pre-reticle using a first illumination system. A second pattern is formed from the second pre-reticle using a second illumination system. An overlay error is measured between the first pattern and the second pattern. A corrected reticle is formed based on the measured overlay error. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, the method comprising: providing a first pre-reticle including a first overlay mark and a first on-cell pattern; providing a second pre-reticle including a second overlay mark and a second on-cell pattern; forming a first pattern from the first pre-reticle using a first illumination system; forming a second pattern from the second pre-reticle using a second illumination system; measuring an overlay error between the first pattern and the second pattern; and forming a corrected reticle based on the measured overlay error. ### Claim 2 (depends on 1) The method of claim 1, wherein the first pattern and the second pattern are formed at different vertical levels from each other. ### Claim 3 (depends on 1) The method of claim 1, wherein a first pitch of the first pattern is different from a second pitch of the second pattern. ### Claim 4 (depends on 1) The method of claim 1, further comprising, after forming the first pattern and the second pattern, adjusting a condition for measuring the overlay error. ### Claim 5 (depends on 1) The method of claim 1, wherein measuring of the overlay error includes measuring the overlay using After Development Inspection. ### Claim 6 (depends on 1) The method of claim 1, further comprising, after measuring the overlay error, obtaining a first average overlay value in a first direction; and obtaining a second average overlay value in a second direction intersecting the first direction. ### Claim 7 (depends on 6) The method of claim 6, wherein the forming of the corrected reticle includes forming the corrected reticle using the obtained first average overlay value and the obtained second average overlay value. ### Claim 8 (depends on 1) The method of claim 1, wherein the second pattern includes photoresist, wherein the first pattern includes a conductive material. ### Claim 9 (depends on 1) The method of claim 1, wherein the first illumination system uses a laser light source, and the second illumination system uses an EUV light source. ### Claim 10 A method for manufacturing a semiconductor device, the method comprising: providing a pre-reticle including an overlay mark and an on-cell pattern; forming an overlay measurement stack from the pre-reticle, wherein the overlay measurement stack includes a lower pattern and an upper pattern; measuring an overlay error between the lower pattern and the upper pattern; and forming a corrected reticle based on the measured overlay error, wherein the forming of the overlay measurement stack includes: forming the lower pattern from a first pre-reticle using a first illumination system; and forming the upper pattern on top of the lower pattern from a second pre-reticle using a second illumination system. ### Claim 11 (depends on 10) The method of claim 10, wherein the forming of the overlay measurement stack further includes forming a light-transmissive film between the lower pattern and the upper pattern. ### Claim 12 (depends on 10) The method of claim 10, further comprising, after forming the overlay measurement stack, adjusting a condition for measuring the overlay error. ### Claim 13 (depends on 10) The method of claim 10, further comprising, after measuring the overlay error, obtaining a first average overlay value in a first direction; and obtaining a second average overlay value in a second direction intersecting the first direction. ### Claim 14 (depends on 13) The method of claim 13, wherein the forming of the corrected reticle includes forming the corrected reticle using the obtained first average overlay value and the obtained second average overlay value. ### Claim 15 (depends on 10) The method of claim 10, wherein: the upper pattern includes photoresist; and the lower pattern includes polysilicon. ### Claim 16 A method for manufacturing a semiconductor device, the method comprising: providing a first pre-reticle including first overlay marks; providing a second pre-reticle including second overlay marks; forming an overlay measurement wafer from the first and second pre-reticles, wherein the overlay measurement wafer includes a lower pattern and an upper pattern; measuring an overlay error between the lower pattern and the upper pattern; and forming a corrected reticle based on the measured overlay error, wherein the forming of the overlay measurement wafer includes: forming the lower pattern from the first pre-reticle using a first illumination system of a first cell pattern; forming a light-transmissive film on the lower pattern; and forming an upper pattern on the light-transmissive film from the second pre-reticle using a second illumination system of a second cell pattern. ### Claim 17 (depends on 16) The method of claim 16, wherein the forming of the overlay measurement wafer includes: forming the lower pattern by performing a first exposure process using the first illumination system; and forming the upper pattern by performing a second exposure process using the second illumination system. ### Claim 18 (depends on 16) The method of claim 16, further comprising, after forming the overlay measurement wafer, adjusting a condition for measuring the overlay error. ### Claim 19 (depends on 16) The method of claim 16, wherein the light-transmissive film includes oxide. ### Claim 20 (depends on 16) The method of claim 16, further comprising, after measuring the overlay, obtaining a first average overlay value in a first direction; and obtaining a second average overlay value in a second direction intersecting the first direction, wherein the forming of the corrected reticle includes forming the corrected reticle using the obtained first average overlay value and the obtained second average overlay value.