Implementation of leakage-tolerant logic gates

Abstract

A logic gate circuit, comprising a logic block for performing logic operations between inputs of the logic block and a restoration block, connected between the output of the logic block and the output of the logic gate, for compensating for voltage level losses when the output being in a high logic state. The logic block discharges the voltage that corresponds to the high logic state to ground, following logic operations that entail a low logic state, via an inherent or a designed current leakage path in the components implementing the logic block.

Dependencies are inferred from the claim text.