US 2025/0141355 A1 · SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING SEMICONDUCTOR DEVICE

Abstract

A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.

Claims19

Dependent claims

(canceled)

A semiconductor device comprising:

a first transistor;
a second transistor;
an oscillator;
a first wiring;
a second wiring;
a first circuit;
a secondary battery;
and
a comparator,
wherein the oscillator is electrically connected to each of the first wiring, the second wiring, and the first circuit,
wherein each of the first transistor and the second transistor comprises a metal oxide comprising indium in a channel formation region,
wherein the oscillator comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,
wherein a gate of the third transistor and a gate of the fourth transistor are electrically connected to one of a source and a drain of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor and a first electrode of the first capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor and a second electrode of the first capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first circuit and a gate of the fifth transistor,
wherein the first wiring is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor,
wherein one of a non-inverting input terminal and an inverting input terminal of the comparator is electrically connected to a positive electrode of the secondary battery, and
wherein the other of the non-inverting input terminal and the inverting input terminal of the comparator is electrically connected to one of a source and a drain of the second transistor.

17 more elements

A semiconductor device comprising:

a first transistor;
a second transistor;
an oscillator;
a first wiring;
a second wiring;
a first circuit;
a secondary battery;
and
a comparator,
wherein the oscillator is electrically connected to each of the first wiring, the second wiring, and the first circuit,
wherein each of the first transistor and the second transistor comprises a metal oxide comprising indium in a channel formation region,
wherein the oscillator comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,
wherein a gate of the third transistor and a gate of the fourth transistor are electrically connected to one of a source and a drain of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor and a first electrode of the first capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor and a second electrode of the first capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first circuit and a gate of the fifth transistor,
wherein the first wiring is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor,
wherein one of a non-inverting input terminal and an inverting input terminal of the comparator is electrically connected to a positive electrode of the secondary battery,
wherein the other of the non-inverting input terminal and the inverting input terminal of the comparator is electrically connected to one of a source and a drain of the second transistor,
wherein the second transistor is configured so that a first potential is supplied to the other of the non-inverting input terminal and the inverting input terminal when the second transistor is turned on,
wherein the second transistor is configured so that the first potential is held at the other of the non-inverting input terminal and the inverting input terminal when the second transistor is turned off,
wherein the comparator is configured to output an output signal based on a result of comparison between a potential of the positive electrode and the first potential, and
wherein the oscillator is configured to block current flowing between the first wiring and the second wiring in accordance with the output signal.

21 more elements

A semiconductor device comprising:

a first transistor;
a second transistor;
an oscillator;
a first wiring;
a second wiring;
a first circuit;
a secondary battery;
and
a comparator,
wherein the oscillator is electrically connected to each of the first wiring, the second wiring, and the first circuit,
wherein each of the first transistor and the second transistor comprises a metal oxide comprising indium in a channel formation region,
wherein the oscillator comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,
wherein a gate of the third transistor and a gate of the fourth transistor are electrically connected to one of a source and a drain of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor and a first electrode of the first capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor and a second electrode of the first capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first circuit and a gate of the fifth transistor,
wherein the first wiring is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor,
wherein one of a non-inverting input terminal and an inverting input terminal of the comparator is electrically connected to a positive electrode of the secondary battery,
wherein the other of the non-inverting input terminal and the inverting input terminal of the comparator is electrically connected to one of a source and a drain of the second transistor,
wherein the first circuit comprises at least one of an inverter and a buffer, and an input terminal,
wherein the gate of the fifth transistor is electrically connected to the input terminal, and
wherein the first circuit is configured to perform at least one of shaping and amplification on a signal supplied to the input terminal.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/986,896Filed 19 Dec 2024

Priority

JP 2019-1258725 Jul 2019

Published

1 May 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

H02M 3/003
Conversion of DC power input into DC power output: constructional details, e.g. physical layout, assembly, wiring or busbar connections
H02M 3/156
Using semiconductor devices only: with automatic control of output voltage or current, e.g. switching regulators
H02H 7/18
Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection…:…
H03K 3/354
By the use, as active elements, of field-effect transistors with internal or external positive feedback: astable circuits

Semiconductor device and method for operating semiconductor device

Life of this patent

Semiconductor device and method for operating semiconductor device

Life of this patent

Abstract

Claims19