Active-discharge control in fail safe state

An inverter circuit, comprising:

• a first phase circuit including:
• a first transistor;
• a first gate driver configured to control the first transistor;
• a second transistor connected in series with the first transistor;
• and
• a second gate driver configured to control the second transistor;
• a microcontroller unit (MCU) configured to produce a first control signal and a second control signal to control an operation of the first gate driver and the second gate driver, respectively, wherein the first control signal and second control signal are configured to control a discharge of a charging capacitor connected to the first phase circuit;
• and
• a power management circuit configured to:
• detect a failure in an operation of the MCU;
• and
• produce a third control signal and a fourth control signal to control the operation of the first gate driver and the second gate driver to control the discharge of the charging capacitor when the failure in the operation of the MCU is detected.

An inverter circuit, comprising:

• a first, second, and third phase circuit, wherein each phase circuit includes:
• a first transistor;
• a first gate driver configured to control the first transistor;
• a second transistor connected in series with the first transistor;
• a second gate driver configured to control the second transistor;
• a microcontroller unit (MCU) configured to produce a first control signal and a second control signal to control an operation of the first gate drivers and the second gate drivers, respectively, wherein the first control signal and second control signal are configured to control a discharge of a charging capacitor connected to the first phase circuit;
• and
• a power management circuit configured to:
• detect a failure in an operation of the MCU;
• and
• produce a third control signal and a fourth control signal to control the operation of the first gate drivers and the second gate drivers to control the discharge of the charging capacitor when the failure in the operation of the MCU is detected.