Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip comprising:
• a first upper conductive pad on an upper surface of the first semiconductor chip;
• a first lower conductive pad on a lower surface of the first semiconductor chip;
• and
• a first through via connected to the first upper conductive pad and the first lower conductive pad;
• a second semiconductor chip, a third semiconductor chip, a fourth semiconductor chip, and a fifth semiconductor chip sequentially stacked on the first semiconductor chip, wherein the second semiconductor chip comprises:
• a second upper conductive pad on an upper surface of the second semiconductor chip;
• and
• a second lower conductive pad on a lower surface of the second semiconductor chip;
• and
• a first bonding structure between the first semiconductor chip and the second semiconductor chip, wherein the first bonding structure comprises:
• the first upper conductive pad;
• the second lower conductive pad;
• a protective metal layer between the first upper conductive pad and the second lower conductive pad;
• an intermetallic compound in the protective metal layer;
• and
• a diffusion barrier surrounding the first upper conductive pad and the second lower conductive pad,
• wherein the protective metal layer covers a surface of the first upper conductive pad and a surface of the second lower conductive pad,
• wherein the upper surface of the first semiconductor chip and the lower surface of the second semiconductor chip directly contact each other,
• wherein the semiconductor package further comprises a first interface between the first semiconductor chip and the second semiconductor chip and a second interface between the protective metal layer and the second lower conductive pad, and
• wherein a first level of the first interface is equal to or lower than a second level of the second interface.

A semiconductor package comprising:

• a package substrate;
• an interposer substrate on the package substrate;
• at least one semiconductor chip structure on the interposer substrate;
• internal connection members connecting the interposer substrate and the at least one semiconductor chip structure;
• and
• a mold layer at least partially covering the interposer substrate and the at least one semiconductor chip structure,
• wherein the at least one semiconductor chip structure comprises:
• a first semiconductor chip;
• second semiconductor chips on the first semiconductor chip, the second semiconductor chips comprising a lowermost second semiconductor chip;
• and
• a bonding structure between the first semiconductor chip and the lowermost second semiconductor chip,
• wherein the bonding structure comprises:
• a first conductive pad on an upper surface of the first semiconductor chip;
• a second conductive pad on a lower surface of the lowermost second semiconductor chip;
• a protective metal layer between the first conductive pad and the second conductive pad;
• and
• an intermetallic compound in the protective metal layer,
• wherein the protective metal layer covers a surface of the first conductive pad and a surface of the second conductive pad,
• wherein the upper surface of the first semiconductor chip and the lower surface of the chip structure directly contact each other,
• wherein the at least one semiconductor chip structure comprises a first interface between the first semiconductor chip and the second conductive pad and a second interface between the protective metal layer and the second conductive pad, and
• wherein a first level of the first interface is equal to or lower than a second level of the second interface.