Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains
AssigneeMicron Technology, Inc.
InventorSteven Jeffrey Wallach
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Abstract
Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.
Claims20
A device, comprising:
- a plurality of memory regions;
- and
- a processor configured to execute a plurality of groups of instructions, wherein the groups of instructions are configured to be in a plurality of domains for execution in the processor;
- wherein the device is configured to, during execution of an instruction in the processor to access a memory region among the plurality of memory regions:
- determine a domain, among the plurality of domains, for the execution of the instruction in the processor;
- and
- determine, based on a permission setting for the domain, whether to provide access to the memory region in connection with the execution of the instruction in the processor.
A method, comprising:
- grouping instructions into a plurality of groups of instructions;
- classifying the plurality of groups of instructions into a plurality of domains for execution in a processor;
- and
- during execution of an instruction in the processor to access a memory region among a plurality of memory regions:
- determining a domain, among the plurality of domains, for the execution of the instruction in the processor based on a group that contains the instruction;
- and
- determining, based on a permission setting for the domain, whether to provide access to the memory region in connection with the execution of the instruction in the processor.
A processor, comprising:
- a plurality of execution units configured to execute instructions, wherein instructions to be executed in the processor are grouped into a plurality of groups of instructions, and wherein the plurality of groups of instructions are classified into a plurality of domains for execution in the processor;
- and
- a memory management unit configured to compute physical memory addresses from virtual memory addresses used by instructions being executed in the processor;
- wherein the processor is configured to, during execution of an instruction in the processor to access a memory region among a plurality of memory regions:
- determine a domain, among the plurality of domains, for the execution of the instruction in the processor based on the instruction being included in one of the plurality of groups;
- and
- determine, based on a permission setting for the domain, whether to provide access to the memory region in connection with the execution of the instruction in the processor.
Dependencies are inferred from the claim text.