Performing cyclic redundancy checks using parallel computing architectures
AssigneeNVIDIA Corporation
InventorAndrea Miele
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.
Claims20
A graphics processor comprising:
- one or more circuits to perform error detection on one or more fifth generation (5G) new radio signals in parallel.
A machine-readable medium having stored thereon a set of instructions, which if performed by one or more graphics processors, cause the one or more graphics processors to perform error detection on one or more fifth generation (5G) new radio signals in parallel.
A system, comprising:
- one or more computers having one or more graphics processors to perform error detection on one or more fifth generation (5G) new radio signals in parallel.
Dependencies are inferred from the claim text.