Decoding Method, Chip, and Related Apparatus

A chip comprising:

• an interface circuit configured to receive code instructions and transmit the code instructions;
• and
• a processing circuit coupled to the interface circuit, wherein the code instructions, when executed by the processing circuit, cause the chip to:
• read a first bit sequence, wherein the first bit sequence comprises n pieces of bit data;
• obtain a check matrix H of the first bit sequence;
• obtain a first syndrome S1 based on the first bit sequence and the check matrix H;
• determine, based on the first bit sequence and the first syndrome S1, a first quantity of check equations that are in the check matrix H and that are not met by each of the n pieces of bit data when the first syndrome S1 is not an all-zero (all-0) value;
• flip first bit data in the first bit sequence to obtain a second bit sequence when the first quantity of check equations that are that are not met by the first bit data is greater than or equal to a first threshold T1;
• obtain, after obtaining the second bit sequence, a second syndrome S2 based on the second bit sequence and the check matrix H;
• obtain, based on the second bit sequence, the second syndrome S2, and a first regular term, a second quantity of check equations that are in the check matrix H and that are not met by each piece of bit data in the second bit sequence when the second syndrome S2 is not the all-0 value, wherein the first regular term is less than or equal to 0;
• flip second bit data in the second bit sequence to obtain a third bit sequence when the second quantity of check equations that are not met by the second bit data is greater than or equal to a second threshold T2;
• obtain, after obtaining the third bit sequence, a third syndrome S3 based on the third bit sequence and the check matrix H;
• and
• output the third bit sequence when the third syndrome S3 is the all-0 value.

A decoding apparatus comprising:

• a memory is configured to store code instructions;
• and
• a processing circuit coupled to the memory, wherein the code instructions, when executed by the processing circuit, cause the decoding apparatus to:
• read a first bit sequence, wherein the first bit sequence comprises n pieces of bit data;
• obtain a check matrix H of the first bit sequence;
• obtain a first syndrome S1 based on the first bit sequence and the check matrix H;
• determine, based on the first bit sequence and the first syndrome S1, a first quantity of check equations that are in the check matrix H and that are not met by each of the n pieces of bit data when the first syndrome S1 is not an all zero (all-0) value;
• flip first bit data in the first bit sequence to obtain a second bit sequence when the first quantity of check equations that are not met by the first bit data is greater than or equal to a first threshold T1;
• obtain, after obtaining the second bit sequence, a second syndrome S2 based on the second bit sequence and the check matrix H;
• obtain, based on the second bit sequence, the second syndrome S2, and a first regular term, a second quantity of check equations that are in the check matrix H and that are not met by each piece of bit data in the second bit sequence when the second syndrome S2 is not the all-0 value, wherein the first regular term is less than or equal to 0;
• flip second bit data in the second bit sequence to obtain a third bit sequence when the second quantity of check equations that are in the check matrix H and that are not met by the second bit data is greater than or equal to a second threshold T2;
• obtain, after obtaining the third bit sequence, a third syndrome S3 based on the third bit sequence and the check matrix H;
• and
• output the third bit sequence when the third syndrome S3 is the all-0 value.

A computer program product comprising computer-executable instructions that are stored on a non-transitory computer-readable storage medium and that, when executed by a processing circuit, cause a chip to:

• read a first bit sequence, wherein the first bit sequence comprises n pieces of bit data;
• obtain a check matrix H of the first bit sequence;
• obtain a first syndrome S1 based on the first bit sequence and the check matrix H;
• determine, based on the first bit sequence and the first syndrome S1, a first quantity of check equations that are in the check matrix H and that are not met by each piece of bit data in the first bit sequence when the first syndrome S1 is not an all-0 value;
• flip first bit data in the first bit sequence to obtain a second bit sequence when the first quantity of check equations that are not met by the first bit data is greater than or equal to a first threshold T1;
• obtain, after obtaining the second bit sequence, a second syndrome S2 based on the second bit sequence and the check matrix H;
• obtain, based on the second bit sequence, the second syndrome S2, and a first regular term, a second quantity of check equations that are in the check matrix H and that are not met by each piece of bit data in the second bit sequence when the second syndrome S2 is not the all-0 value, wherein the first regular term is less than or equal to 0;
• flip second bit data in the second bit sequence to a third bit sequence when the second quantity of check equations and that are not met by the second bit data is greater than or equal to a second threshold T2;
• obtain, after obtaining the third bit sequence, a third syndrome S3 based on the third bit sequence and the check matrix H;
• and
• output the third bit sequence when the third syndrome S3 is the all-0 value.