# US 2025/0125199 A1 · Wafer level testing of optical components > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0125199 A1 - Document ID: US20250125199A1 - Status: Published application - Kind: A1 - Application number: 18/987,403 - Filed: 2024-12-19 - Published: 2025-04-17 - Earliest claimed: 2018-07-20 - Assignees: II-Vi Delaware, Inc. - Applicants: II-VI Delaware, Inc. - Inventors: Shiyun LIN; Daniel MAHGEREFTEH; Bryan PARK; Jin-Hyoung LEE - Web page: https://patentgrep.com/patent/US20250125199A1 ## CPC - G01N 21/9501: {Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20)} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)} - G01R 31/311: of integrated circuits {(G01R31/31728 takes precedence)} - G02B 1/11: Anti-reflection coatings - G02B 6/13: Integrated optical circuits characterised by the manufacturing method - G02B 6/4214: {the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device (G02B6/4246 takes precedence)} - H10P 74/27: {Structural arrangements therefor} - G01N 2021/9511: {Optical elements other than lenses, e.g. mirrors} - G02B 6/34: utilising prism or grating {(G02B6/293 takes precedence)} - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS ## Abstract A system may include a wafer that includes ICs and defines cavities. Each cavity may be formed in a BEOL layer of the wafer and proximate a different IC. The system may also include an interposer that includes a transparent layer configured to permit optical signals to pass through. The interposer may also include at least one waveguide located proximate the transparent layer. The at least one waveguide may be configured to adiabatically couple at least one optical signal out of the multiple ICs. Further, the interposer may include a redirecting element optically coupled to the at least one the waveguide. The redirecting element may be located proximate the transparent layer and may be configured to receive the at least one optical signal from the at least one waveguide. The redirecting element may also be configured to vertically redirect the at least one optical signal towards the transparent layer. ## Claims ### Claim at position 1 1-20. (canceled) ### Claim 21 A system comprising: a wafer comprising a plurality of chips, the wafer defining a plurality of cavities, two adjacent chips of the plurality of chips sharing at least one cavity of the plurality of cavities, the adjacent chips having at least one dicing lane between the adjacent chips within the cavity; and an interposer configured to test the plurality of chips, the interposer being sized to removably fit at least partially within the at least one cavity, the interposer comprising: at least one waveguide, the at least one waveguide configured to adiabatically couple at least one optical signal between the adjacent chips. ### Claim 22 (depends on 21) The system of claim 21, wherein the interposer crosses the at least one dicing lane when the interposer is fit within the respective cavity. ### Claim 23 (depends on 21) The system of claim 21, wherein the two adjacent chips each comprise at least one adiabatic coupler adjacent to the dicing lane. ### Claim 24 (depends on 23) The system of claim 23, wherein the dicing lane is adjacent an edge of at least one of the adiabatic couplers and is adapted such that dicing along the dicing lane would expose the edge of the least one adiabatic coupler. ### Claim 25 (depends on 23) The system of claim 23, wherein the respective at least one adiabatic coupler of the two adjacent chips optically align with the at least one waveguide of the interposer when the interposer is fit within the respective cavity. ### Claim 26 (depends on 21) The system of claim 21, wherein at least one of the two adjacent chips comprises a curved waveguide, the curved waveguide having a first end and a second end, each of the first end and the second end intersecting the dicing lane. ### Claim 27 (depends on 21) The system of claim 21, wherein the two adjacent chips comprise at least one adiabatic coupler at least partially overlapping with the respective cavity ### Claim 28 (depends on 21) The system of claim 21, wherein the interposer comprises a plurality of waveguides and at least one of the two adjacent chips comprises a plurality of adiabatic couplers adapted to optically align with the plurality of waveguides of the interposer when the interposer is fit within the respective cavity. ### Claim 29 (depends on 28) The system of claim 28, wherein the two adjacent chips comprise at least one transmit port and at least one receive port. ### Claim 30 (depends on 28) The system of claim 28, wherein the plurality of adiabatic couplers within the at least one of the two adjacent chips are adapted to optically connect to each other through the interposer when the interposer is fit within the respective cavity. ### Claim 31 (depends on 21) The system of claim 21, wherein the interposer is removably bonded to the wafer. ### Claim 32 (depends on 21) The system of claim 21, the interposer further comprising: a transparent layer and a redirecting element optically coupled to the at least one waveguide and adapted to provide at least one redirected optical signal. ### Claim 33 (depends on 32) The system of claim 32, further comprising an optical component located proximate the transparent layer, the optical component configured to receive the at least one redirected optical signal. ### Claim 34 (depends on 33) The system of claim 33, wherein the optical component is configured to provide an electrical signal to an external device, the electrical signal representative of the at least one redirected optical signal. ### Claim 35 (depends on 21) The system of claim 21, wherein each cavity of the plurality of cavities are formed in a back end of line (BEOL) layer of the wafer. ### Claim 36 (depends on 23) The system of claim 23, wherein the plurality of cavities are formed in the wafer such that a portion of a front end of line (FEOL) layer of the wafer is located above the at least one adiabatic coupler in each chip of the plurality of chips and the portion of the FEOL layer is thin enough to enable optical coupling between the at least one adiabatic coupler and the at least one waveguide of the interposer. ### Claim 37 (depends on 32) The system of claim 32, wherein: the redirecting element comprises a grating coupler. ### Claim 38 (depends on 32) The system of claim 32, wherein the redirecting element comprises a mirror. ### Claim 39 (depends on 32) The system of claim 32, the interposer further comprising: an anti-reflection (AR) coating located on a top surface of the transparent layer. ### Claim 40 (depends on 21) The system of claim 21, wherein each IC of the plurality of ICs comprise at least one of a photonic integrated circuit and an optical integrated circuit.