Memory device and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJung-Piao Chiu, Yu-Sheng Chen
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Abstract
A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.
Claims20
A semiconductor die, having a logic region and a memory region disposed at an edge of the logic region, and comprising:
- a logic device, located in the logic region;
- and
- a memory device, located in the memory region, electrically coupled to the logic device and comprising:
- first word lines on a first level and extending in a first direction;
- second word lines on a second level below the first level and extending in a second direction different from the first direction;
- and
- bit lines extending in a third direction different from the first and second directions, and the bit lines being interposed between two neighboring first word lines of the first word lines and between two neighboring second word lines of the second word lines.
A semiconductor die, comprising
- a semiconductor substrate;
- an interconnect structure disposed over the semiconductor substrate;
- and
- a memory device comprising:
- a memory cell array embedded in the interconnect structure and comprising:
- first word line branches connected together through a first common connection and disposed on a first tier of the memory cell array, the first word line branches extending in a first direction, and the first common connection extending in a second direction different from the first direction;
- second word line branches connected together through a second common connection and disposed on a second tier of the memory cell array, the second word line branches extending in the second direction, and the second common connection extending in the first direction;
- and
- bit lines extending in a third direction different from the first and second directions and passing through the first and second tiers of the memory cell array.
A semiconductor die, comprising:
- a semiconductor substrate;
- an interconnect structure disposed over the semiconductor substrate;
- and
- a memory device embedded in the interconnect structure and comprising:
- first-tier word lines extending in a first direction;
- second-tier word lines disposed above the first-tier word lines and extending in a second direction angularly offset from the first direction, each of the second-tier word lines comprising overlapping regions and non-overlapping regions alternately arranged in the first and second directions, wherein each of the overlapping regions overlaps one of the first-tier word lines;
- and
- bit lines extending in a third direction angularly offset from the first and second directions, and the bit lines adjoining the non-overlapping regions.
Dependencies are inferred from the claim text.