Rank-based dot product circuitry
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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Abstract
Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper offset. Each partial product may have an associated one's to two's complement conversion bit. The conversion bits of the various partial product groups can be separately aggregated and then injected into the compressor tree at one or more locations.
Claims20
An integrated circuit device comprising:
- a partial product generation circuit to receive input operands and output corresponding partial products;
- a first compressor circuit to receive a first group of the partial products all having a first rank and output first vectors;
- a second compressor circuit to receive a second group of the partial products all having a second rank different from the first rank and output second vectors;
- and
- an adder circuit to output a dot product value based at least in part on the first vectors and the second vectors.
An integrated circuit comprising:
- a plurality of compressor circuits to respectively compress a group of partial products all having the same rank and output a plurality of vectors, wherein the group of partial products are grouped based on rank and not shifted prior to compression;
- and
- at least one adder to output a sum of the plurality of vectors.
An application-specific integrated circuit (ASIC) comprising:
- a first compressor circuit to receive a first group of partial products all having a first rank and output first vectors;
- a second compressor circuit to receive a second group of partial products all having a second rank different from the first rank and output second vectors;
- a first shifting circuit to shift the second vectors relative to the first vectors;
- and
- a third compressor circuit to compress the first vectors and the shifted second vectors and output third vectors.
Dependencies are inferred from the claim text.