Signal Sampling Circuitry and A Method for Signal Sampling and Holding
OwnerEwout Martens, Anirudh Praveen Kankuppe Raghavendra Swamy +1inventors
InventorsEwout Martens, Anirudh Praveen Kankuppe Raghavendra Swamy, Angelo Parisi
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Abstract
A signal sampling circuitry comprises: a plurality of sampling units receiving an input signal for time-interleaved sampling, each sampling unit comprising: a sampling capacitor having a first plate connected to an output of the sampling unit; a first plate switch between the first plate and a first reference voltage, a second plate switch between a second plate of the sampling capacitor and a second reference voltage; an input buffer for outputting a buffered input signal to the second plate; wherein the input buffer is connected to at least one power gating switch for powering down the input buffer.
Claims18
A signal sampling circuitry comprising:
- a plurality of sampling units configured to receive an input signal for time-interleaved sampling, wherein each sampling unit of the plurality of sampling units comprises:
- a sampling capacitor having a first plate and a second plate, wherein the first plate is connected to an output of the sampling unit;
- a first plate switch arranged between the first plate of the sampling capacitor and a first reference voltage, wherein the first plate switch is configured to receive a first clock signal at a gate of the first plate switch for controlling the first plate switch between an active state and an inactive state;
- a second plate switch arranged between the second plate of the sampling capacitor and a second reference voltage, wherein the second plate switch is configured to receive a second clock signal at a gate of the second plate switch for controlling the second plate switch between an active state and an inactive state;
- an input buffer configured to receive the input signal and configured to output a buffered input signal at an output node, wherein the output node of the input buffer is connected to the second plate of the sampling capacitor;
- wherein the input buffer is connected to at least one power gating switch for powering down the input buffer.
A method for signal sampling and holding using a plurality of sampling units for time-interleaved sampling, said method comprising, by each sampling unit of the plurality of sampling units:
- receiving the input signal at an input buffer;
- controlling the input buffer to be active;
- providing a buffered input signal from the input buffer at a second plate of a sampling capacitor;
- providing a sampled output signal at an output of the sampling unit connected to a first plate of the sampling capacitor, by opening a first plate switch between the first plate of the sampling capacitor and a first reference voltage;
- thereafter holding the sampled output signal at the output by closing a second plate switch between the second plate of the sample capacitor and a second reference voltage;
- and
- powering down the input buffer by controlling at least one power gating switch.
Dependencies are inferred from the claim text.