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US 2025/0117271 A1Published application
Processing system with interspersed processors dma-fifo
AssigneeHyperX Logic, Inc.
InventorsCarl S. Dobbs, Michael R. Trocino, Keith M. Bindloss
Life of this patent
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Abstract
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
Claims20
A multi-processor system, comprising:
- a plurality of processors, each comprising a plurality of processor ports;
- and
- a plurality of configurable communication elements coupled to the plurality of processors in an interspersed fashion, wherein each configurable communication element comprises:
- a plurality of communication ports;
- a routing engine coupled to the plurality of communication ports;
- a plurality of memories, wherein each memory of the plurality of memories is coupled to a subset of processors of the plurality of processors;
- a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is coupled to a respective one of the plurality of communication ports;
- wherein a first DMA engine of the plurality of DMA engines is configured to calculate a first signature for at least a first portion of a first memory of the plurality of memories;
- wherein a second DMA engine of the plurality of DMA engines is configured to calculate a second signature for at least a second portion of the first memory of the plurality of memories;
- and
- wherein a particular processor of the plurality of processors is configured to compare the first signature and the second signature.
8 more elements
A method for operating a multiprocessor system, the method comprising:
- executing at least one program on a plurality of processors, each processor including at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports;
- wherein executing the at least one program includes:
- calculating, by a first direct memory access (DMA) engine of a plurality of DMA engines, a first signature for at least a first portion of a first memory of a plurality of memories, wherein each memory of the plurality of memories is coupled to a respective subset of the plurality of processors;
- calculating, by a second DMA engine of the plurality of DMA engines, a second signature for at least a second portion of the first memory of the plurality of memories;
- and
- comparing the first signature and the second signature.
3 more elements
An apparatus, comprising:
- a plurality of processors, each comprising a plurality of processor ports, wherein the plurality of processors is configured to execute at least one program;
- a plurality of memories coupled to the plurality of processors in an interspersed fashion;
- a plurality of configurable communication elements that each include a plurality of communication ports and a routing engine;
- a plurality of direct memory access (DMA) engines, wherein each DMA engine of the plurality of DMA engines is coupled to a respective one of the plurality of communication ports;
- wherein, in executing the at least one program, the plurality of processors are configured to:
- calculate, by a first DMA engine of the plurality of DMA engines, a first signature for at least a first portion of a first memory of the plurality of memories;
- calculate, by a second DMA engine of the plurality of DMA engines, a second signature for at least a second portion of the first memory of the plurality of memories;
- and
- wherein a particular processor of the plurality of processors is configured to compare the first signature and the second signature.
6 more elements
Dependencies are inferred from the claim text.