Processors employing default tags for writes to memory from devices not compliant with a memory tagging extension and related methods

A processing circuit configured to couple to a memory circuit, the processing circuit configured to:

• execute a memory access instruction to access a first memory address of the memory circuit;
• and
• in response to executing the memory access instruction:
• receive, from the memory circuit, first tag bits associated with the first memory address;
• determine that the first tag bits are different than second tag bits in the memory access instruction;
• and
• in response to a mode indicator indicating a first mode, compare the first tag bits to default tag bits.

A method in a system including a processing circuit coupled to a memory circuit, the method comprising:

• executing a memory access instruction to access a first memory address of the memory circuit;
• and
• in response to executing the memory access instruction:
• accessing first tag bits associated with the first memory address;
• determining that the first tag bits are different than second tag bits in the memory access instruction;
• and
• in response to a mode indicator indicating a first mode, comparing the first tag bits to default tag bits.